Miodrag Milanovic
35d28de478
Visual Studio build fix
2019-07-31 09:10:24 +02:00
Bogdan Vukobratovic
c075486c59
Reimplement opt_share to work on $alu and $pmux
2019-07-28 16:03:54 +02:00
Eddie Hung
07e38d8d5c
Update test_autotb doc to reflect default value of zero
2019-07-26 12:37:30 -07:00
Eddie Hung
8cecad5059
Add doc for "test_autotb -seed" option
2019-07-26 12:26:54 -07:00
Eddie Hung
4c25d1a76f
Pop the CO bit from O
2019-07-26 10:27:30 -07:00
Eddie Hung
c1a05f4557
Allow adders/accumulators with 33 bits using CO output
2019-07-26 10:15:36 -07:00
Bogdan Vukobratovic
07c4a7d438
Implement opt_share
...
This pass identifies arithmetic operators that share an operand and whose
results are used in mutually exclusive cases controlled by a multiplexer, and
merges them together by multiplexing the other operands
2019-07-26 11:36:48 +02:00
Eddie Hung
79fd6edc5a
Eliminate warnings by sizing O correctly
2019-07-23 15:13:30 -07:00
Eddie Hung
a37574ccbf
Fix muxAB logic
2019-07-23 14:52:14 -07:00
Eddie Hung
0dd2a125f6
Remove debug print
2019-07-23 14:21:45 -07:00
Eddie Hung
dc0c853abe
Simplify and fix for MACs
2019-07-23 14:20:34 -07:00
Eddie Hung
4f11ff8ebd
Fix typo
2019-07-23 13:58:56 -07:00
Eddie Hung
33c984a044
Fix spacing
2019-07-22 16:37:13 -07:00
Eddie Hung
068617f094
Pack hi and lo registers separately
2019-07-22 16:12:57 -07:00
Eddie Hung
4d71ab384d
Rename according to vendor doc TN1295
2019-07-22 15:08:26 -07:00
Eddie Hung
304cefbbe2
Pack Y register
2019-07-22 15:05:16 -07:00
Eddie Hung
5a14b6e1f6
Pack adders not just accumulators
2019-07-22 13:01:49 -07:00
Clifford Wolf
c6d8692c97
Add "stat -tech cmos"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-07-20 15:06:28 +02:00
Eddie Hung
e0720a8018
Restore old ffY behaviour
2019-07-19 22:47:08 -07:00
Eddie Hung
f9d08a5e5e
Cleanup
2019-07-19 20:25:28 -07:00
Eddie Hung
09beeee38a
Try and fix again
2019-07-19 14:40:57 -07:00
Eddie Hung
e87916b7eb
Merge remote-tracking branch 'origin/eddie/wreduce_add' into ice40dsp
2019-07-19 14:03:34 -07:00
Eddie Hung
cb0fd05215
Do not access beyond bounds
2019-07-19 13:58:50 -07:00
Eddie Hung
3a87dc3524
Wrap A and B in sigmap
2019-07-19 13:23:07 -07:00
Eddie Hung
31b0002e8c
Remove "top" from message
2019-07-19 13:20:45 -07:00
Eddie Hung
8791e0caac
Merge remote-tracking branch 'origin/eddie/wreduce_add' into ice40dsp
2019-07-19 13:18:20 -07:00
Eddie Hung
bcd8027182
Also optimise MSB of $sub
2019-07-19 13:11:48 -07:00
Eddie Hung
fc0e36d1c0
wreduce for $sub
2019-07-19 12:50:21 -07:00
Eddie Hung
9ad11ea2cc
Fine tune ice40_dsp.pmg, add support for packing subsets of registers
2019-07-19 10:57:32 -07:00
Eddie Hung
8f0e796be1
Add support for ice40 signed multipliers
2019-07-19 10:38:13 -07:00
Eddie Hung
42e40dbd0a
Merge remote-tracking branch 'origin/master' into ice40dsp
2019-07-18 15:45:25 -07:00
Eddie Hung
09411dd996
ice40_dsp to accept $__MUL16X16 too
2019-07-18 15:38:28 -07:00
Eddie Hung
802470746c
Check if RHS is empty first
2019-07-18 15:22:00 -07:00
Eddie Hung
90ac147eb2
Do not autoremove ffP aor muxP
2019-07-18 15:02:41 -07:00
Eddie Hung
08fe63c61e
Improve pattern matcher to match subsets of $dffe? cells
2019-07-18 14:08:18 -07:00
Eddie Hung
79d63479ea
Improve A/B reg packing
2019-07-18 13:30:35 -07:00
Eddie Hung
e075f0dda0
Do not autoremove A/B registers since they might have other consumers
2019-07-18 13:22:22 -07:00
Eddie Hung
0727b2c902
Fix xilinx_dsp index cast
2019-07-18 13:18:04 -07:00
Eddie Hung
c76607b9bc
Wrong wildcard symbol
2019-07-18 08:14:58 -07:00
Eddie Hung
91629ee4b3
Pattern matcher to check pool of bits, not exactly
2019-07-17 12:45:25 -07:00
Eddie Hung
3f677fb0db
Signed extension
2019-07-16 15:54:07 -07:00
Eddie Hung
9616dbd125
Add support {A,B,P}REG packing
2019-07-16 14:06:32 -07:00
Eddie Hung
5939b5d636
Merge pull request #1188 from YosysHQ/eddie/abc9_push_inverters
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abc9: push inverters driving box inputs (comb outputs) through $lut soft logic
2019-07-16 08:53:47 -07:00
Eddie Hung
ba8ccbdea8
Merge pull request #1186 from YosysHQ/eddie/abc9_ice40_fix
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abc9/ice40: encapsulate SB_CARRY+SB_LUT4 into one box
2019-07-16 08:52:14 -07:00
Miodrag Milanovic
2b469e82a7
Fix check logic in extract_fa
2019-07-16 10:35:18 +02:00
Eddie Hung
5f00d335d4
Oops forgot these files
2019-07-15 15:03:15 -07:00
Eddie Hung
dd59375a66
Add xilinx_dsp for register packing
2019-07-15 14:46:31 -07:00
Clifford Wolf
2a7198db51
Merge pull request #1189 from YosysHQ/eddie/fix1151
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Error out if enable > dbits in memory_bram file
2019-07-15 20:06:35 +02:00
Clifford Wolf
2c5c53e4c1
Merge pull request #1190 from YosysHQ/eddie/fix_1099
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extract_fa to return nothing more gracefully
2019-07-15 20:05:56 +02:00
whitequark
2de7e92bb8
opt_lut: make less chatty.
2019-07-13 16:49:56 +00:00
Eddie Hung
9b91d815b5
If ConstEval fails do not log_abort() but return gracefully
2019-07-13 04:13:57 -07:00
Eddie Hung
ab3917d079
Error out if enable > dbits
2019-07-13 03:39:23 -07:00
Eddie Hung
fb062c3426
Add comment
2019-07-13 00:52:21 -07:00
Eddie Hung
e9bdc86c0e
duplicate -> clone
2019-07-12 19:33:02 -07:00
Eddie Hung
be0cb7f4b8
More cleanup
2019-07-12 19:30:18 -07:00
Eddie Hung
7d583f9e57
Cleanup
2019-07-12 19:30:18 -07:00
Eddie Hung
83f23a24a8
Cleanup
2019-07-12 19:30:18 -07:00
Eddie Hung
1adbfb5533
Cleanup
2019-07-12 19:30:18 -07:00
Eddie Hung
39a7c7c54c
More cleanup
2019-07-12 19:30:18 -07:00
Eddie Hung
91c07be196
Cleanup
2019-07-12 19:30:18 -07:00
Eddie Hung
399e1ec870
Cleanup
2019-07-12 19:30:18 -07:00
Eddie Hung
58dbb28fd3
Cleanup
2019-07-12 19:30:18 -07:00
Eddie Hung
7dc15bdd2d
Do not double count cells in abc
2019-07-12 08:22:26 -07:00
Eddie Hung
237d8651a5
Error out if abc9 not called with -lut or -luts
2019-07-11 09:58:00 -07:00
Eddie Hung
0c3ed73dad
Count $_NOT_ cells turned into $luts
2019-07-11 09:55:14 -07:00
Eddie Hung
33862d0445
WIP for fixing partitioning, temporarily do not partition
2019-07-11 09:22:52 -07:00
Eddie Hung
c0abd18799
Enable &mfs for abc9, even if it only currently works for ice40
2019-07-11 08:49:06 -07:00
Clifford Wolf
fd3d5cefad
Merge pull request #1179 from whitequark/attrmap-proc
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attrmap: also consider process, switch and case attributes
2019-07-11 07:23:28 +02:00
Eddie Hung
9f608d6be3
write_verilog with *.v extension
2019-07-10 20:25:59 -07:00
Eddie Hung
71acd3ddcf
Remove -retime from abc9, revert to abc behav with separate clock/en domains
2019-07-10 18:57:44 -07:00
Eddie Hung
052060f109
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-07-10 16:05:41 -07:00
whitequark
ea447220da
attrmap: also consider process, switch and case attributes.
2019-07-10 12:30:53 +00:00
Clifford Wolf
c66b4b9131
Merge pull request #1177 from YosysHQ/clifford/async
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Fix clk2fflogic adff reset semantic to negative hold time on reset
2019-07-10 08:48:20 +02:00
Clifford Wolf
cae26bf330
Merge pull request #1174 from YosysHQ/eddie/fix1173
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Increment _TECHMAP_BITS_CONNMAP_ by one since counting from zero
2019-07-09 22:59:51 +02:00
Clifford Wolf
9546ccdbd3
Fix tests/various/async FFL test
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-07-09 22:44:39 +02:00
Eddie Hung
c2db70f41e
Increment _TECHMAP_BITS_CONNMAP_ by one since counting from zero
2019-07-09 12:14:00 -07:00
Eddie Hung
713337255e
Revert "Add "synth -keepdc" option"
2019-07-09 10:14:23 -07:00
Clifford Wolf
e95ce1f7af
Merge pull request #1168 from whitequark/bugpoint-processes
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Add support for processes in bugpoint
2019-07-09 16:59:43 +02:00
Clifford Wolf
a0787c12f0
Merge pull request #1169 from whitequark/more-proc-cleanups
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A new proc_prune pass
2019-07-09 16:59:18 +02:00
Clifford Wolf
38e942507e
Merge pull request #1163 from whitequark/more-case-attrs
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More support for case rule attributes
2019-07-09 16:57:16 +02:00
whitequark
44bcb7a187
proc_prune: promote assigns to module connections when legal.
...
This can pave the way for further transformations by exposing
identities that were previously hidden in a process to any pass that
uses SigMap. Indeed, this commit removes some ad-hoc logic from
proc_init that appears to have been tailored to the output of
genrtlil in favor of using `SigMap.apply()`. (This removal is not
optional, as the ad-hoc logic cannot cope with the result of running
proc_prune; a similar issue was fixed in proc_arst.)
2019-07-09 09:30:58 +00:00
whitequark
5fe0ffe30f
proc_prune: new pass.
...
The proc_prune pass is similar in nature to proc_rmdead pass: while
proc_rmdead removes branches that never become active because another
branch preempts it, proc_prune removes assignments that never become
active because another assignment preempts them.
Genrtlil contains logic similar to the proc_prune pass, but their
purpose is different: genrtlil has to prune assignments to adapt
the semantics of blocking assignments in HDLs (latest assignment
wins) to semantics of assignments in RTLIL processes (assignment in
the most specific case wins). On the other hand proc_prune is
a general purpose RTLIL simplification that benefits all frontends,
even those not using the Yosys AST library.
The proc_prune pass is added to the proc script after proc_rmdead,
since it gives better results with fewer branches.
2019-07-09 09:30:58 +00:00
whitequark
f2fb958d44
bugpoint: add -assigns and -updates options.
2019-07-09 09:27:43 +00:00
whitequark
f7a14a5678
proc_clean: add -quiet option.
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This is useful for other passes that call it often, like bugpoint.
2019-07-09 09:27:43 +00:00
Eddie Hung
37b58f4324
Clarify 'wreduce -keepdc' doc
2019-07-08 19:15:07 -07:00
Eddie Hung
b5072256f2
Update muxcover doc as per @ZirconiumX
2019-07-08 12:50:59 -07:00
Eddie Hung
3681162c8d
atoi -> stoi
2019-07-08 11:00:06 -07:00
Eddie Hung
a34c5612e7
Add muxcover -mux2=cost option
2019-07-08 10:59:12 -07:00
whitequark
48655dfb8b
proc_mux: consider \src attribute on CaseRule.
2019-07-08 13:18:18 +00:00
Eddie Hung
35fd9b0473
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-07-02 12:35:45 -07:00
David Shah
d45936fe5f
memory_dff: Fix checking of feedback mux input when more than one mux
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Signed-off-by: David Shah <dave@ds0.me>
2019-07-02 13:35:50 +01:00
Eddie Hung
ef757002db
Also remove $__ABC_FF_
2019-07-01 10:55:24 -07:00
Eddie Hung
699d8e3939
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-07-01 10:44:42 -07:00
Gabriel L. Somlo
8cb3655ecd
Make abc9 pass aware of optional ABCEXTERNAL override
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Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-06-28 14:56:16 -04:00
Eddie Hung
4a2a93aa06
Fix spacing
2019-06-28 11:10:36 -07:00
Eddie Hung
da5f830395
Merge pull request #1098 from YosysHQ/xaig
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"abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
2019-06-28 10:59:03 -07:00
Clifford Wolf
1c7ce251f3
Merge pull request #1046 from bogdanvuk/master
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Optimizing DFFs whose initial value prevents their value from changing
2019-06-28 08:30:18 +02:00
Eddie Hung
a625854ac5
Do not use Module::remove() iterator version
2019-06-27 15:29:20 -07:00
Eddie Hung
137c91d9a9
Remove &retime when abc9 -fast
2019-06-27 15:17:39 -07:00
Eddie Hung
6bf73e3546
Cleanup abc9.cc
2019-06-27 15:15:56 -07:00
Bogdan Vukobratovic
3225bfb984
Add help for "-sat" option inside opt_rmdff. "opt" can pass "-sat" too
2019-06-27 22:06:23 +02:00
Bogdan Vukobratovic
35fa7b3057
Fix memory leak when one of multiple DFF cells is removed in opt_rmdff
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When there are multiple DFFs and one of them is removed, its reference lingers
inside bit2driver dict. While invoking handle_dff() function for other DFFs,
this broken reference is used isnside sat_import_cell() function.
2019-06-27 22:02:12 +02:00
Eddie Hung
440f173aef
Merge remote-tracking branch 'origin/master' into xaig
2019-06-27 11:54:34 -07:00
Eddie Hung
6c210e5813
Merge pull request #1143 from YosysHQ/clifford/fix1135
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Add "pmux2shiftx -norange"
2019-06-27 11:48:48 -07:00
Eddie Hung
6c256b8cda
Merge origin/master
2019-06-27 11:20:15 -07:00
Bogdan Vukobratovic
0f32cb4e0a
Merge remote-tracking branch 'upstream/master'
2019-06-27 12:11:47 +02:00
Clifford Wolf
7c14678ec0
Add "pmux2shiftx -norange", fixes #1135
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-27 10:59:12 +02:00
Clifford Wolf
69d810e4a8
Fix handling of partial covers in muxcover, fixes #1132
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-27 09:42:58 +02:00
Eddie Hung
c226af3f56
Fix spacing
2019-06-26 20:03:34 -07:00
Eddie Hung
26efd6f0a9
Support more than one port in the abc_scc_break attr
2019-06-26 19:57:54 -07:00
Clifford Wolf
0b7d648c6a
Improve opt_clean handling of unused public wires
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-26 17:54:17 +02:00
Clifford Wolf
8e9ef891fe
Do not clean up buffer cells with "keep" attribute, closes #1128
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-26 11:01:03 +02:00
Eddie Hung
5db96b8aec
Missing muxpack.o in Makefile
2019-06-25 10:38:42 -07:00
Eddie Hung
6f36ec8ecf
Merge remote-tracking branch 'origin/master' into xaig
2019-06-25 09:33:11 -07:00
Clifford Wolf
add2d415fc
Merge pull request #1130 from YosysHQ/eddie/fix710
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memory_dff: walk through more than one mux for computing read enable
2019-06-25 17:34:44 +02:00
Eddie Hung
42720ef6fe
Fix spacing
2019-06-25 08:33:17 -07:00
Eddie Hung
c4e4902098
Move only one consumer check outside of while loop
2019-06-25 08:29:55 -07:00
Eddie Hung
d2fed0a7f1
nullptr check
2019-06-25 06:06:32 -07:00
Eddie Hung
a19226c174
Fix for abc_scc_break is bus
2019-06-24 22:16:56 -07:00
Eddie Hung
5605002d8a
More meaningful error message
2019-06-24 22:12:55 -07:00
Eddie Hung
babadf5938
Do not use log_id as it strips \\, also fix scc for |wire| > 1
2019-06-24 22:04:22 -07:00
Eddie Hung
49a762ba46
Fix abc9's scc breaker, also break on abc_scc_break attr
2019-06-24 21:53:18 -07:00
Eddie Hung
b7deaceadd
Walk through as many muxes as exist for rd_en
2019-06-24 18:33:06 -07:00
Eddie Hung
4ddc0354c1
Merge remote-tracking branch 'origin/master' into eddie/muxpack
2019-06-22 14:40:55 -07:00
Eddie Hung
1abe93e48d
Merge remote-tracking branch 'origin/master' into xaig
2019-06-21 17:43:29 -07:00
Eddie Hung
ad296d77ab
Do not rename non LUT cells in abc9
2019-06-21 17:18:04 -07:00
Eddie Hung
e01bab6c64
Merge pull request #1108 from YosysHQ/clifford/fix1091
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Add support for partial matches to muxcover
2019-06-21 17:13:41 -07:00
Eddie Hung
545cfbbe0d
Cope with $reduce_or common in case
2019-06-21 12:31:14 -07:00
Eddie Hung
15535112b7
Fix spacing
2019-06-21 11:52:51 -07:00
Eddie Hung
d89d663c92
Add doc
2019-06-21 11:52:28 -07:00
Eddie Hung
641b86d25f
Fix up ExclusiveDatabase with @cliffordwolf's help
2019-06-21 11:45:31 -07:00
Eddie Hung
63eb5cace9
Merge branch 'master' into eddie/muxpack
2019-06-21 11:17:19 -07:00
Clifford Wolf
ec979475e7
Replace "muxcover -freedecode" with "muxcover -dmux=cost"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-21 19:24:41 +02:00
Eddie Hung
6d74cf0d2b
Merge pull request #1085 from YosysHQ/eddie/shregmap_improve
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Improve shregmap to handle case where first flop is common to two chains
2019-06-21 08:56:56 -07:00
Clifford Wolf
c9949dba99
Merge pull request #1117 from bwidawsk/more-home
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Add a few more filename rewrites
2019-06-21 10:13:51 +02:00
Clifford Wolf
9286b6f013
Add "muxcover -freedecode"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-21 10:02:10 +02:00
Eddie Hung
54f3237720
Fix gcc warning of potentially uninitialised
2019-06-20 22:10:43 -07:00
Clifford Wolf
891ea6512e
Improvements in muxcover
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- Slightly under-estimate cost of decoder muxes
- Prefer larger muxes at tree root at same cost
- Don't double-count input cost for partial muxes
- Add debug log output
2019-06-20 19:47:59 -07:00
Clifford Wolf
40188457d1
Add support for partial matches to muxcover, fixes #1091
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-20 19:47:59 -07:00
Eddie Hung
0e97e6a00d
Fix simple_abc9/generate test with 1'bx at MSB
2019-06-20 19:41:27 -07:00
Eddie Hung
e612dade12
Merge remote-tracking branch 'origin/master' into xaig
2019-06-20 19:00:36 -07:00
Eddie Hung
3f34779d64
Do not call "setundef -zero" in abc9
2019-06-20 17:38:04 -07:00
Eddie Hung
e63324f5ef
Actually, there might not be any harm in updating sigmap...
2019-06-20 17:03:05 -07:00
Eddie Hung
9c61fb0e0c
Add comment as per @cliffordwolf
2019-06-20 16:57:54 -07:00
Ben Widawsky
8767ec3fbd
Add a few more filename rewrites
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This now allows a full pipeline to work, something such as:
yosys -p "synth_ecp5 -json ~/work/fpga/prjtrellis/examples/ecp5_evn/blinky.v"
Otherwise, you will get something along the lines of:
ERROR: Can't open output file `~/work/fpga/prjtrellis/examples/ecp5_evn/blinky.v' for writing: No such file or directory
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2019-06-20 10:27:59 -07:00
Clifford Wolf
477e566e8d
Fix typo, fixes #1095
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-20 15:34:52 +02:00
Clifford Wolf
06eb87bcb7
Improve shregmap help message, fixes #1113
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-20 15:23:55 +02:00
Clifford Wolf
2454ad99bf
Refactor "opt_rmdff -sat"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-20 13:44:21 +02:00
Clifford Wolf
73bd1d59a7
Merge branch 'master' of https://github.com/bogdanvuk/yosys into clifford/ext1046
2019-06-20 13:04:04 +02:00
Clifford Wolf
11ec7b2aec
Fix typo
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-20 12:23:07 +02:00
acw1251
0d888ee7ed
Fixed the help summary line for a few commands
2019-06-19 15:27:04 -04:00
Eddie Hung
96ade54993
Fix bug in #1078 , add entry to CHANGELOG
2019-06-19 09:51:11 -07:00
Clifford Wolf
3da5288ce0
Use input default values in hierarchy pass
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-19 11:49:20 +02:00
Eddie Hung
d80678e581
Cleanup
2019-06-17 15:10:33 -07:00
Eddie Hung
3ebba74461
Merge branch 'xaig' into xaig_dff
2019-06-17 13:51:53 -07:00
Eddie Hung
4d6d593fe3
&scorr before &sweep, remove &retime as recommended
2019-06-17 13:32:08 -07:00
Eddie Hung
a474fe937b
Merge branch 'xaig' into xaig_dff
2019-06-17 13:20:19 -07:00
Eddie Hung
63fc879a5f
Copy not move parameters/attributes
2019-06-17 13:19:45 -07:00
Eddie Hung
7dd3a7f161
Merge branch 'xaig' into xaig_dff
2019-06-17 12:58:41 -07:00
Eddie Hung
b45d06d7a3
Fix leak removing cells during ABC integration; also preserve attr
2019-06-17 12:54:24 -07:00
Eddie Hung
5ce672d1c5
Merge remote-tracking branch 'origin/xaig' into xaig_dff
2019-06-17 12:14:55 -07:00
Eddie Hung
7250c57c5a
Re-enable &dc2
2019-06-17 10:28:51 -07:00
Eddie Hung
fb90d8c18c
Cleanup
2019-06-16 09:34:26 -07:00
Eddie Hung
3ed95dae8d
Cleanup
2019-06-15 22:48:16 -07:00
Eddie Hung
416312b9ed
abc9 to recover_init by default
2019-06-15 22:44:45 -07:00
Eddie Hung
2309459605
Do not treat $__ABC_FF_ as a user cell
2019-06-15 19:36:55 -07:00
Eddie Hung
cdfb634977
Cleanup
2019-06-15 18:18:56 -07:00
Eddie Hung
c2f3f116d0
Use $__ABC_FF_ instead of $_FF_
2019-06-15 18:16:14 -07:00
Eddie Hung
a76c8a7ffd
Fix initialisation of flops
2019-06-15 09:46:35 -07:00
Eddie Hung
ac18a76beb
Map to $_FF_ instead of $_DFF_P_ to prevent recursion issues
2019-06-15 09:34:48 -07:00
Eddie Hung
da487c4f31
For now, short $_DFF_[NP]_ from ff_map.v at re-integration
2019-06-15 09:08:18 -07:00
Eddie Hung
2d85725604
Get rid of compiler warnings
2019-06-14 13:07:56 -07:00
Eddie Hung
a632799d5b
Update abc9 -D doc
2019-06-14 12:29:46 -07:00
Eddie Hung
e391fc8e7b
Enable "abc9 -D <num>" for timing-driven synthesis
2019-06-14 12:28:01 -07:00
Eddie Hung
a48b5bfaa5
Further cleanup based on @daveshah1
2019-06-14 12:25:06 -07:00
Eddie Hung
751e640c1d
Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig
2019-06-14 10:29:16 -07:00
Eddie Hung
a5425a2f7e
Remove extra semicolon
2019-06-14 10:11:34 -07:00
David Shah
9566573054
ecp5: Add abc9 option
...
Signed-off-by: David Shah <dave@ds0.me>
2019-06-14 17:15:02 +01:00
Bogdan Vukobratovic
8451cbea89
Move netlist helper module to passes/opt for the time being
2019-06-14 12:14:02 +02:00
Bogdan Vukobratovic
fe651922cb
Merge remote-tracking branch 'upstream/master'
2019-06-14 12:06:57 +02:00
Bogdan Vukobratovic
53695e6729
Prepare for situation when port of the signal cannot be found
2019-06-14 11:39:24 +02:00
Bogdan Vukobratovic
291b36afeb
Some cleanup, revert sat.cc
2019-06-14 11:35:45 +02:00
Bogdan Vukobratovic
8665f48879
Implement disconnection of constant register bits
2019-06-13 19:35:37 +02:00
Eddie Hung
2c40b66785
Rip out all non FPGA stuff from abc9
2019-06-12 16:53:12 -07:00
Eddie Hung
f81a189fb8
Fix spelling
2019-06-12 16:52:09 -07:00
Eddie Hung
90dc4d82de
Revert "For 'stat' do not count modules with abc_box_id"
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This reverts commit b89bb74452
.
2019-06-12 16:51:37 -07:00
Eddie Hung
b3faf0246d
Be more precise when connecting during ABC9 re-integration
2019-06-12 16:04:33 -07:00
Eddie Hung
2e7e73f483
Remove hacky wideports_split from abc9
2019-06-12 15:52:49 -07:00
Eddie Hung
d9974b85e7
Fix compile errors when #if 1 for debug
2019-06-12 15:47:39 -07:00
Bogdan Vukobratovic
d69989b8d2
Rename satgen_algo.h -> algo.h, code cleanup and refactoring
2019-06-12 19:35:05 +02:00
Eddie Hung
8bb67fa67c
Do not call abc9 if no outputs
2019-06-12 10:18:44 -07:00
Eddie Hung
14e870d4c4
More write_xaiger cleanup
2019-06-12 10:00:57 -07:00
Eddie Hung
b21d29598a
Consistency
2019-06-12 09:40:51 -07:00
Eddie Hung
b2c72f74f0
Merge branch 'xc7mux' into xaig
2019-06-12 09:14:27 -07:00
Eddie Hung
afd620fd5f
Typo: wire delay is -W argument
2019-06-12 09:13:53 -07:00
Eddie Hung
2cbcd6224c
Revert "Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux"
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This reverts commit a138381ac3
, reversing
changes made to b77c5da769
.
2019-06-12 09:05:02 -07:00
Eddie Hung
882a83c383
Revert "Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux"
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This reverts commit eaee250a6e
, reversing
changes made to 935df3569b
.
2019-06-12 09:04:31 -07:00
Eddie Hung
86efe9a616
Revert "Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux"
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This reverts commit 2223ca91b0
, reversing
changes made to eaee250a6e
.
2019-06-12 09:01:15 -07:00
Eddie Hung
1e838a8913
Retry "Add "-W' wire delay arg to abc9, use from synth_xilinx"
2019-06-12 08:49:15 -07:00
Eddie Hung
4c9fde87d1
Revert "Add "-W' wire delay arg to abc9, use from synth_xilinx"
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This reverts commit 2dffa4685b
.
2019-06-12 08:48:45 -07:00
Eddie Hung
2dffa4685b
Add "-W' wire delay arg to abc9, use from synth_xilinx
2019-06-11 17:10:47 -07:00
Eddie Hung
6cdea93724
Revert "Try way that doesn't involve creating a new wire"
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This reverts commit 2f427acc9e
.
2019-06-11 16:05:42 -07:00
Eddie Hung
d26646051c
Revert "Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux"
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This reverts commit 5174082208
, reversing
changes made to 54379f9872
.
2019-06-11 16:05:27 -07:00
Eddie Hung
5174082208
Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux
2019-06-11 15:48:41 -07:00
Eddie Hung
2f427acc9e
Try way that doesn't involve creating a new wire
2019-06-11 15:48:20 -07:00
Bogdan Vukobratovic
9892df17ef
Generate satgen instance instead of calling sat pass
2019-06-11 11:47:13 +02:00
Eddie Hung
a138381ac3
Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux
2019-06-10 16:21:43 -07:00
Eddie Hung
f19aa8d989
If d_bit already in sigbit_chain_next, create extra wire
2019-06-10 16:16:40 -07:00
Eddie Hung
a1d4ae78a0
Revert "Rename shregmap -tech xilinx -> xilinx_dynamic"
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This reverts commit 94a5f4e609
.
2019-06-10 14:34:43 -07:00
Eddie Hung
7d27e1e431
Revert "shregmap -tech xilinx_dynamic to work -params and -enpol"
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This reverts commit 45d1bdf83a
.
2019-06-10 14:34:16 -07:00
Eddie Hung
3579d68193
Revert "Refactor to ShregmapTechXilinx7Static"
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This reverts commit e1e37db860
.
2019-06-10 14:34:15 -07:00
Eddie Hung
b6a39351f4
Revert "Add -tech xilinx_static"
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This reverts commit dfe9d95579
.
2019-06-10 14:34:14 -07:00
Eddie Hung
e1dbeb3004
Revert "Continue support for ShregmapTechXilinx7Static"
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This reverts commit 72eda94a66
.
2019-06-10 14:34:14 -07:00
Eddie Hung
9d8563178e
Revert "shregmap -tech xilinx_static to handle INIT"
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This reverts commit 935df3569b
.
2019-06-10 14:34:12 -07:00
Eddie Hung
5b999ae68d
Elaborate muxpack doc
2019-06-10 10:32:19 -07:00
Eddie Hung
1dd7e23a20
Merge remote-tracking branch 'origin/master' into eddie/muxpack
2019-06-10 10:28:40 -07:00
Eddie Hung
5a46a0b385
Fine tune aigerparse
2019-06-07 16:57:32 -07:00
Eddie Hung
f705f6a0b5
Comment O(N) -> O(N^2)
2019-06-07 15:39:12 -07:00
Eddie Hung
ba52d9b471
Extend ExclusiveDatabase to query SigSpec-s (for $pmux)
2019-06-07 15:34:16 -07:00
Eddie Hung
9b408838f1
Add ExclusiveDatabase to check exclusive $eq/$logic_not cell results
2019-06-07 14:18:17 -07:00
Eddie Hung
887df8914c
Resolve @cliffordwolf comment on redundant check
2019-06-07 11:37:52 -07:00
Eddie Hung
5ab59cd59e
Resolve @cliffordwolf comment on sigmap
2019-06-07 11:36:19 -07:00
Eddie Hung
30abdaf3b2
Allow muxcover costs to be changed
2019-06-07 08:34:11 -07:00
Eddie Hung
fe4394fb9a
Allow muxcover costs to be changed
2019-06-07 08:30:39 -07:00
Eddie Hung
2223ca91b0
Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux
2019-06-06 14:22:10 -07:00
Eddie Hung
5c277c6325
Fix and test for balanced case
2019-06-06 14:21:34 -07:00
Eddie Hung
eaee250a6e
Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux
2019-06-06 14:06:59 -07:00
Eddie Hung
ccdf989025
Support cascading $pmux.A with $mux.A and $mux.B
2019-06-06 13:51:22 -07:00
Eddie Hung
dc7b8c4b94
More cleanup
2019-06-06 12:56:34 -07:00
Eddie Hung
978fda94f6
Fix spacing
2019-06-06 12:46:42 -07:00
Eddie Hung
d2172c6846
Non chain user check using next_sig
2019-06-06 12:44:50 -07:00
Eddie Hung
83450a9489
Move muxpack from passes/techmap to passes/opt
2019-06-06 12:15:13 -07:00
Eddie Hung
3dd0682f29
Update doc
2019-06-06 12:11:59 -07:00
Eddie Hung
3e76e3a6fa
Add tests, fix for !=
2019-06-06 11:54:38 -07:00
Eddie Hung
543dd11c7e
Missing file
2019-06-06 11:03:45 -07:00
Eddie Hung
7bd1c664a6
Initial adaptation of muxpack from shregmap
2019-06-06 10:51:02 -07:00
Clifford Wolf
e4e1cd6930
Merge pull request #1071 from YosysHQ/eddie/fix_1070
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Fix typo in opt_rmdff causing register to be incorrectly removed
2019-06-06 06:50:12 +02:00
Clifford Wolf
50e2dce5e7
Merge pull request #1072 from YosysHQ/eddie/fix_1069
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Error out if no top module given before 'sim'
2019-06-06 06:49:07 +02:00
Eddie Hung
fd8ef128bf
Missing doc for -tech xilinx in shregmap
2019-06-05 14:21:44 -07:00
Eddie Hung
dd134914cc
Error out if no top module given before 'sim'
2019-06-05 14:16:24 -07:00
Eddie Hung
feb2ddb52b
Fix typo in opt_rmdff
2019-06-05 14:08:14 -07:00
Eddie Hung
935df3569b
shregmap -tech xilinx_static to handle INIT
2019-06-05 12:55:59 -07:00
Eddie Hung
72eda94a66
Continue support for ShregmapTechXilinx7Static
2019-06-05 12:33:55 -07:00
Eddie Hung
dfe9d95579
Add -tech xilinx_static
2019-06-05 11:14:14 -07:00
Eddie Hung
e1e37db860
Refactor to ShregmapTechXilinx7Static
2019-06-05 11:08:08 -07:00
Eddie Hung
45d1bdf83a
shregmap -tech xilinx_dynamic to work -params and -enpol
2019-06-05 10:21:57 -07:00
Eddie Hung
a3a80b755c
Merge pull request #1067 from YosysHQ/clifford/fix1065
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Suppress driver-driver conflict warning for unknown cell types
2019-06-05 09:59:05 -07:00
Eddie Hung
bcc0a5d136
Merge remote-tracking branch 'origin/master' into xc7mux
2019-06-05 09:56:57 -07:00
Eddie Hung
b5aff1de04
Merge remote-tracking branch 'origin/clifford/fix1065' into xc7mux
2019-06-05 09:56:51 -07:00
Clifford Wolf
b33176dafb
Major rewrite of wire selection in setundef -init
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-05 10:26:48 +02:00
Clifford Wolf
6cc60ffd67
Indent fix
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-05 09:53:06 +02:00
Clifford Wolf
00d32eb73d
Merge pull request #999 from jakobwenzel/setundefInitFix
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initialize more registers in setundef -init
2019-06-05 09:50:15 +02:00
Clifford Wolf
4190d7c094
Fix typo in fmcombine log message, fixes #1063
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-05 09:26:44 +02:00
Clifford Wolf
8a6f9977f6
Suppress driver-driver conflict warning for unknown cell types, fixes #1065
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-05 09:14:12 +02:00
Eddie Hung
94a5f4e609
Rename shregmap -tech xilinx -> xilinx_dynamic
2019-06-04 14:34:36 -07:00
Eddie Hung
f81a0ed92e
Merge remote-tracking branch 'origin/master' into xc7mux
2019-06-03 23:07:08 -07:00
Eddie Hung
295bd8d0bf
Remove dupe
2019-06-03 12:32:20 -07:00
Eddie Hung
eb08e71bd1
Merge branch 'xaig' into xc7mux
2019-05-31 13:03:03 -07:00
Eddie Hung
a379234f56
Throw out unused code inherited from abc
2019-05-31 12:50:11 -07:00
Clifford Wolf
90ec2cda42
Fix "tee" handling of log_streams
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-31 09:28:51 +02:00
Eddie Hung
4a6b9af227
Fix spelling
2019-05-30 15:50:47 -07:00
Eddie Hung
a44fe3a632
Revert "Re-enable &dc2"
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This reverts commit 8c58c728a7
.
2019-05-30 11:41:50 -07:00
Eddie Hung
0800846e73
Do not double count LUT1s
2019-05-30 11:32:14 -07:00
Eddie Hung
8c58c728a7
Re-enable &dc2
2019-05-30 00:42:41 -07:00
Eddie Hung
2560f92f29
Reduce -W to 160
2019-05-29 23:01:46 -07:00
Eddie Hung
854557814e
Erase all boxes before stitching
2019-05-29 19:17:36 -07:00
Eddie Hung
b955344ecd
Call &if with -W 250
2019-05-29 16:34:52 -07:00
Eddie Hung
ecaa7856e9
Add some debug to abc9
2019-05-29 15:21:41 -07:00
Clifford Wolf
349c47250a
Merge pull request #1049 from YosysHQ/clifford/fix1047
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Do not use shiftmul peepopt pattern when mul result is truncated
2019-05-28 19:02:26 +02:00
Eddie Hung
cdedf51c32
From master
2019-05-28 09:37:50 -07:00
Eddie Hung
914074a07c
Update from master
2019-05-28 09:35:45 -07:00
Eddie Hung
ba9513b325
Merge remote-tracking branch 'origin/master' into xc7mux
2019-05-28 09:30:53 -07:00
Eddie Hung
4a76b425cc
Misspell
2019-05-28 08:44:59 -07:00
Clifford Wolf
cb285e4b87
Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-28 17:17:56 +02:00
Clifford Wolf
ba2185ead8
Refactor hierarchy wand/wor handling
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-28 16:43:25 +02:00
Bogdan Vukobratovic
29a78267d7
Fix the regression
2019-05-28 15:45:04 +02:00
Bogdan Vukobratovic
9a468f81c4
Optimizing DFFs whose initial value prevents their value from changing
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This is a proof of concept implementation that invokes SAT solver via Pass::call
method.
2019-05-28 08:48:21 +02:00
Eddie Hung
89bd6b8504
If driver not found, use LUT2
2019-05-27 23:12:21 -07:00
Eddie Hung
4df37c77fd
Disconnect all ABC boxes too
2019-05-27 19:40:27 -07:00
Eddie Hung
75bd41eaeb
Parse without wideports
2019-05-27 12:22:05 -07:00
Eddie Hung
bf3b8d5e45
Remove mapped_mod when done
2019-05-27 12:19:21 -07:00
Eddie Hung
234156c01a
Instantiate cell type (from sym file) otherwise 'clean' warnings
2019-05-27 12:16:10 -07:00
Eddie Hung
03b289a851
Add 'cinput' and 'coutput' to symbols file for boxes
2019-05-27 11:38:52 -07:00
Stefan Biereigel
816082d5a1
Merge branch 'master' into wandwor
2019-05-27 19:07:46 +02:00
Stefan Biereigel
ed625a3102
move wand/wor resolution into hierarchy pass
2019-05-27 18:00:22 +02:00
Clifford Wolf
2a9c68e2d6
Merge pull request #1026 from YosysHQ/clifford/fix1023
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Keep zero-width wires in opt_clean if and only if they are ports
2019-05-27 13:24:19 +02:00
Eddie Hung
3981eba999
ABC9 to call &sweep
2019-05-26 11:31:35 -07:00
Eddie Hung
086b6560b4
Typo
2019-05-26 03:17:20 -07:00
Eddie Hung
823153e418
Combine ABC_COMMAND_LUT
2019-05-26 02:47:06 -07:00
Eddie Hung
32a4c10c0d
Fix "a" extension
2019-05-26 02:44:36 -07:00
Eddie Hung
d4fb6cac7c
Revert enable check
2019-05-25 12:55:57 -07:00
Eddie Hung
822d0b7789
opt_rmdff to optimise even in presence of enable signal, even removing
2019-05-24 18:30:51 -07:00
Eddie Hung
0d66103cbb
Add comments
2019-05-24 16:33:10 -07:00
Eddie Hung
357b1de6bc
Resolve @cliffordwolf review, set even if !has_init
2019-05-24 16:15:22 -07:00
Eddie Hung
6ad09bfcea
Add &fraig and &mfs back
2019-05-24 15:10:18 -07:00
Eddie Hung
68359bcd6f
Merge remote-tracking branch 'origin/eddie/opt_rmdff' into xc7mux
2019-05-23 13:37:53 -07:00
Eddie Hung
5ac7e38d0a
Fix spacing
2019-05-23 12:58:30 -07:00
Eddie Hung
50ed34a6d0
opt_rmdff to work on $dffe and $_DFFE_*
2019-05-23 11:26:18 -07:00
Clifford Wolf
e3f9ccf56d
Keep zero-width wires in opt_clean if and only if they are ports, fixes #1023
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-22 13:57:36 +02:00
Eddie Hung
fb09c6219b
Merge remote-tracking branch 'origin/master' into xc7mux
2019-05-21 14:21:00 -07:00
Clifford Wolf
c4b8575f43
Add "wreduce -keepdc", fixes #1016
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-20 15:36:13 +02:00
Clifford Wolf
a21a84b3b4
Improvements in opt_clean
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-15 16:01:28 +02:00
Clifford Wolf
f67ec1b235
Do not leak file descriptors in cover.cc
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-15 13:51:02 +02:00
Henner Zeller
5e443a5d0d
Fix two instances of integer-assignment to string.
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o In cover.cc, the int-result of mkstemps() was assigned to a string
and silently interpreted as a single-character filename with a funny
value. Fix with the intent: assign the filename.
o in libparse.cc, an int was assigned to a string, but depending on
visible constructors, this is ambiguous. Explicitly cast this to
a char.
2019-05-14 22:01:15 -07:00
whitequark
c8c1df23a0
bugpoint: check for -script option.
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Fixes #925 .
2019-05-14 10:48:06 +00:00
Clifford Wolf
8166a142dd
Fix handling of glob_abort_cnt in opt_muxtree, fixes #1002
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-12 13:51:12 +02:00
Clifford Wolf
faf00586d8
Merge pull request #1003 from makaimann/zinit-all
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Zinit option '-singleton' -> '-all'
2019-05-11 13:56:51 +02:00
Clifford Wolf
b66b657b6b
Add "fmcombine -initeq -anyeq"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-11 09:28:55 +02:00
Clifford Wolf
04ef222cfb
Add "stat -tech xilinx"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-11 09:24:52 +02:00
Makai Mann
2f5cfa014b
Zinit option '-singleton' -> '-all'
2019-05-10 10:23:14 -07:00
Jakob Wenzel
f06cb75b93
initialize more registers in setundef -init
2019-05-09 12:47:16 +02:00
Clifford Wolf
3870e7cf29
Merge pull request #991 from kristofferkoch/gcc9-warnings
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Fix all warnings that occurred when compiling with gcc9
2019-05-08 11:25:22 +02:00
Kristoffer Ellersgaard Koch
30c762d3a1
Fix all warnings that occurred when compiling with gcc9
2019-05-08 10:27:14 +02:00
Clifford Wolf
a76189e7ad
More opt_clean cleanups
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-07 14:41:58 +02:00
Clifford Wolf
752553d8e9
Merge pull request #946 from YosysHQ/clifford/specify
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Add specify parser
2019-05-06 20:57:15 +02:00
Clifford Wolf
1706798f4e
Merge pull request #975 from YosysHQ/clifford/fix968
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Re-enable "final loop assignment" feature and fix opt_clean warnings
2019-05-06 20:53:38 +02:00
Clifford Wolf
7bab7b3d49
Merge pull request #871 from YosysHQ/verific_import
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Improve verific -chparam and add hierarchy -chparam
2019-05-06 20:51:59 +02:00
Clifford Wolf
d187be39d6
Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968
2019-05-06 15:41:13 +02:00
Clifford Wolf
b37c31e2cb
Bugfix in peepopt_shiftmul.pmg
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-06 15:34:19 +02:00
Clifford Wolf
c0782d8390
Merge pull request #989 from YosysHQ/dave/abc_name_improve
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ABC name recovery fixes
2019-05-06 13:57:35 +02:00
Clifford Wolf
f02e22a35a
Fix bug in "expose -input"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-06 13:30:55 +02:00
Clifford Wolf
ba6ce21a74
Cleanups in opt_clean
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-06 12:45:22 +02:00
Clifford Wolf
c7f2e93024
Merge branch 'master' of github.com:YosysHQ/yosys into clifford/specify
2019-05-06 11:46:10 +02:00
David Shah
a84256aa36
abc: Fix handling of postfixed names (e.g. for retiming)
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Signed-off-by: David Shah <dave@ds0.me>
2019-05-04 17:23:44 +01:00
David Shah
5ce9113eda
abc: Improve name recovery
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Signed-off-by: David Shah <dave@ds0.me>
2019-05-04 16:53:25 +01:00
Clifford Wolf
a01386c0e4
Improve opt_clean handling of unused wires
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-04 09:47:16 +02:00
Eddie Hung
d9c4644e88
Merge remote-tracking branch 'origin/master' into clifford/specify
2019-05-03 15:05:57 -07:00
Clifford Wolf
ec39cfd0ad
Add "hierarchy -chparam" support for non-verific top modules
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-03 22:03:43 +02:00
Eddie Hung
eb21bf3651
log_warning_noprefix -> log_warning as per review
2019-05-03 20:53:25 +02:00
Eddie Hung
a27b42e975
WIP -chparam support for hierarchy when verific
2019-05-03 20:53:25 +02:00
Clifford Wolf
373b236108
Merge pull request #969 from YosysHQ/clifford/pmgenstuff
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Improve pmgen, Add "peepopt" pass with shift-mul pattern
2019-05-03 20:39:50 +02:00
Clifford Wolf
f170fb6383
Merge pull request #984 from YosysHQ/eddie/fix_982
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dffinit to do nothing when (* init *) value is 1'bx
2019-05-03 20:34:32 +02:00
Eddie Hung
e08df0c739
If init is 1'bx, do not add to dict as per @cliffordwolf
2019-05-03 08:06:16 -07:00
Eddie Hung
fc349de033
Revert "dffinit -noreinit to silently continue when init value is 1'bx"
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This reverts commit aa081f83c7
.
2019-05-03 08:05:37 -07:00
Clifford Wolf
42190207b4
Improve opt_expr and opt_clean handling of (partially) undriven and/or unused wires, fixes #981
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-03 14:25:01 +02:00
Clifford Wolf
5c2c0b4bb2
Further improve unused-detection for opt_clean driver-driver conflict warning
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-03 09:22:26 +02:00
Clifford Wolf
f12e1155f1
Improve unused-detection for opt_clean driver-driver conflict warning
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-03 09:12:10 +02:00
Clifford Wolf
2b29aa5c86
Update pmgen documentation
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-03 08:35:45 +02:00
Clifford Wolf
e8c5afcb84
Fix typo
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-03 08:25:30 +02:00
Eddie Hung
aa081f83c7
dffinit -noreinit to silently continue when init value is 1'bx
2019-05-02 17:40:39 -07:00
Eddie Hung
8829cba901
Merge remote-tracking branch 'origin/clifford/pmgenstuff' into xc7mux
2019-05-02 11:25:34 -07:00
Eddie Hung
5cd19b52da
Merge remote-tracking branch 'origin/master' into xc7mux
2019-05-02 10:44:59 -07:00
Eddie Hung
f86d153cef
Merge branch 'master' of github.com:YosysHQ/yosys
2019-05-01 16:26:43 -07:00
Clifford Wolf
521663f09e
Add missing enable_undef to "sat -tempinduct-def", fixes #883
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-02 00:03:31 +02:00
Clifford Wolf
93b7fd7744
Fix floating point exception in qwp, fixes #923
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-01 15:06:46 +02:00
Clifford Wolf
a30b99e66e
Silently resolve completely unused cell-vs-const driver-driver conflicts
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-01 09:29:34 +02:00
Clifford Wolf
32ff37bb5a
Fix segfault in wreduce
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-30 22:20:45 +02:00
Clifford Wolf
a27eeff573
Merge pull request #966 from YosysHQ/clifford/fix956
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Drive dangling wires with init attr with their init value
2019-04-30 18:08:41 +02:00
Clifford Wolf
9d117eba9d
Add handling of init attributes in "opt_expr -undriven"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-30 14:46:12 +02:00
Clifford Wolf
b515fd2d25
Add peepopt_muldiv, fixes #930
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-30 11:25:15 +02:00
Clifford Wolf
4306bebe58
pmgen progress
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-30 10:51:51 +02:00
Clifford Wolf
bb4f3642de
Some pmgen reorg, rename peepopt.pmg to peepopt_shiftmul.pmg
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-30 08:04:22 +02:00
Clifford Wolf
58238da133
Progress in shiftmul peepopt pattern
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-30 07:59:39 +02:00
Clifford Wolf
ea547bcaa3
Add "peepopt" skeleton
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-29 13:38:56 +02:00
Clifford Wolf
9f792c599d
Add pmgen support for multiple patterns in one matcher
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-29 13:02:05 +02:00
Clifford Wolf
32881a989c
Support multiple pmg files (right now just concatenated together)
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-29 12:09:02 +02:00
Clifford Wolf
754b1ee4b3
Drive dangling wires with init attr with their init value, fixes #956
2019-04-29 08:44:53 +02:00
Eddie Hung
acafcdc94d
Copy with 1'bx padding in $shiftx
2019-04-28 13:04:34 -07:00
Eddie Hung
dcc8a13e48
Revert "Merge branch 'eddie/split_shiftx' into xc7mux"
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This reverts commit 3042d58330
, reversing
changes made to feff976454
.
2019-04-26 15:32:02 -07:00
Eddie Hung
159e7cc298
Add -undef option to equiv_opt, passed to equiv_induct
2019-04-26 11:16:48 -07:00
Eddie Hung
4473fd1502
Add -undef option to equiv_opt, passed to equiv_induct
2019-04-26 11:14:33 -07:00
Eddie Hung
976d8030dc
Actually use pm.st.shiftxB
2019-04-25 19:59:33 -07:00
Eddie Hung
fb4348f840
Fix for when B_WIDTH has trailing zeroes
2019-04-25 19:38:19 -07:00
Eddie Hung
880652283c
Merge remote-tracking branch 'origin/eddie/split_shiftx' into xc7mux
2019-04-25 18:52:20 -07:00
Eddie Hung
ece2c49e92
In order to indicate a failed pattern, blacklist?
2019-04-25 18:39:13 -07:00
Eddie Hung
af3c374a35
Elaborate on help message
2019-04-25 17:35:39 -07:00
Eddie Hung
3042d58330
Merge branch 'eddie/split_shiftx' into xc7mux
2019-04-25 17:31:27 -07:00
Eddie Hung
ccd0729456
Add split_shiftx command
2019-04-25 17:23:59 -07:00
Eddie Hung
8d00b9ef7e
Make pmgen support files more generic
2019-04-25 17:23:46 -07:00
Eddie Hung
408161ea3a
Misspelling
2019-04-25 16:46:13 -07:00
Eddie Hung
d9c915042a
Move clean from aigerparse to abc9
2019-04-23 13:42:35 -07:00
Clifford Wolf
71c38d9de5
Add $specrule cells for $setup/$hold/$skew specify rules
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
Clifford Wolf
634482380c
Preserve $specify[23] cells
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
Clifford Wolf
c84cdc711c
Remove some left-over log_dump()
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 17:55:41 +02:00
Eddie Hung
4df4a97ffa
Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig
2019-04-22 18:20:39 -07:00
Eddie Hung
0bd2bfa737
Merge remote-tracking branch 'origin/master' into xaig
2019-04-22 18:15:28 -07:00
Eddie Hung
5f30a8795d
Tidy up
2019-04-22 17:47:05 -07:00
Eddie Hung
d9daf09cf3
Merge pull request #914 from YosysHQ/xc7srl
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synth_xilinx to now infer SRL16E/SRLC32E
2019-04-22 13:31:30 -07:00
Eddie Hung
4cfef7897f
Merge branch 'xaig' into xc7mux
2019-04-22 11:58:59 -07:00
Eddie Hung
4486a98fd5
Merge remote-tracking branch 'origin/xc7srl' into xc7mux
2019-04-22 11:45:49 -07:00
Eddie Hung
4883391b63
Merge remote-tracking branch 'origin/master' into xaig
2019-04-22 11:19:52 -07:00
Clifford Wolf
8ed4a53d99
Merge pull request #951 from YosysHQ/clifford/logdebug
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Add log_debug() framework
2019-04-22 20:09:51 +02:00
Clifford Wolf
1d538ff1ec
Merge pull request #949 from YosysHQ/clifford/pmux2shimprove
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Add full_pmux feature to pmux2shiftx
2019-04-22 20:01:43 +02:00
Eddie Hung
e300b1922c
Merge remote-tracking branch 'origin/master' into xc7srl
2019-04-22 10:36:27 -07:00
Clifford Wolf
e158ea2097
Add log_debug() framework
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-22 17:25:52 +02:00
whitequark
aeeefc32d8
attrmap: extend -remove to allow removing attributes with any value.
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Currently, `-remove foo` would only remove an attribute `foo = ""`,
which doesn't work on an attribute like `src` that may have any
value. Extend `-remove` to handle both cases. `-remove foo=""` has
the old behavior, and `-remove foo` will remove the attribute with
whatever value it may have, which is still compatible with the old
behavior.
2019-04-22 14:18:15 +00:00
Clifford Wolf
0f0ada13f4
Add full_pmux feature to pmux2shiftx
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-22 15:26:20 +02:00
Clifford Wolf
99d5435650
Merge pull request #905 from christian-krieg/feature/python_bindings
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Feature/python bindings
2019-04-22 14:47:52 +02:00
Clifford Wolf
a98b171814
Merge pull request #944 from YosysHQ/clifford/pmux2shiftx
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Add pmux2shiftx command
2019-04-22 08:39:37 +02:00
Eddie Hung
d06d4f35c3
Merge remote-tracking branch 'origin/clifford/libwb' into xaig
2019-04-21 18:10:46 -07:00
Clifford Wolf
7b35d57592
Disable blackbox detection in techmap files
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-22 02:07:36 +02:00
Eddie Hung
d99422411f
Use new pmux2shiftx from #944 , remove my old attempt
2019-04-21 14:16:34 -07:00
Eddie Hung
98781acf84
Merge remote-tracking branch 'origin/clifford/pmux2shiftx' into xc7srl
2019-04-20 17:24:33 -07:00
Eddie Hung
9dc11cd842
Merge remote-tracking branch 'origin/master' into xc7srl
2019-04-20 17:24:06 -07:00
Eddie Hung
caec7f9d2c
Merge remote-tracking branch 'origin/master' into xaig
2019-04-20 12:23:49 -07:00
Clifford Wolf
f84a84e3f1
Merge pull request #943 from YosysHQ/clifford/whitebox
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[WIP] Add "whitebox" attribute, add "read_verilog -wb"
2019-04-20 20:51:54 +02:00
Eddie Hung
b25254020c
Merge remote-tracking branch 'origin/pmux2shiftx' into xc7srl
2019-04-20 10:44:01 -07:00
Eddie Hung
13ad19482f
Merge remote-tracking branch 'origin' into xc7srl
2019-04-20 10:41:43 -07:00
Clifford Wolf
fc23af1707
Auto-initialize OnehotDatabase on-demand in pmux2shiftx.cc
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-20 18:13:37 +02:00
Clifford Wolf
97e9caa4fa
Add "onehot" pass, improve "pmux2shiftx" onehot handling
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-20 17:52:16 +02:00
Clifford Wolf
f3ad8d680a
Add "techmap -wb", use in formal flows
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-20 11:23:24 +02:00
Clifford Wolf
b7445ef387
Check blackbox attribute in techmap/simplemap
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-20 11:10:05 +02:00
Clifford Wolf
5b915f0153
Add "wbflip" command
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-20 11:04:46 +02:00
Clifford Wolf
e3687f6f4e
Merge pull request #942 from YosysHQ/clifford/fix931
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Improve proc full_case detection and handling
2019-04-20 10:05:35 +02:00
Clifford Wolf
b3a3e08e38
Improve "pmux2shiftx"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-20 02:03:44 +02:00
Clifford Wolf
e06d158e8a
Fix some typos
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-20 01:18:07 +02:00
Clifford Wolf
37728520a6
Improvements in "pmux2shiftx"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-20 01:15:48 +02:00
Clifford Wolf
0070184ea9
Improvements in pmux2shiftx
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-20 00:38:25 +02:00
Clifford Wolf
177878cbb0
Improve pmux2shift ctrl permutation finder
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-20 00:38:25 +02:00
Clifford Wolf
481f0015be
Complete rewrite of pmux2shiftx
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-20 00:38:25 +02:00
Clifford Wolf
1bf8c2b823
Import initial pmux2shiftx from eddieh
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-20 00:38:25 +02:00
Clifford Wolf
eafc4bd49f
Improve "show" handling of 0/1/X/Z padding
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-20 00:37:43 +02:00
Eddie Hung
9dec3d9978
Spelling fixes
2019-04-19 14:00:22 +02:00
Eddie Hung
290a798cec
Ignore 'whitebox' attr in flatten with "-wb" option
2019-04-18 10:32:00 -07:00
Eddie Hung
c997a77014
Ignore 'whitebox' attr in flatten with "-wb" option
2019-04-18 10:19:45 -07:00
Eddie Hung
070a2d2fd6
Fix abc's remap_name to not ignore [^0-9] when extracting sid
2019-04-18 09:55:03 -07:00
Eddie Hung
8fe0a961b3
Merge remote-tracking branch 'origin/clifford/whitebox' into xaig
2019-04-18 09:00:06 -07:00
Eddie Hung
9aa94370a5
ABC to call retime all the time
2019-04-18 08:46:41 -07:00
Clifford Wolf
f4abc21d8a
Add "whitebox" attribute, add "read_verilog -wb"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-18 17:45:47 +02:00
Eddie Hung
0642baabbc
Merge branch 'master' into eddie/fix_retime
2019-04-18 07:57:17 -07:00
Clifford Wolf
88be1cbfa5
Improve proc full_case detection and handling, fixes #931
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-18 15:13:47 +02:00
Eddie Hung
a20ed260e1
Skip if abc_box_id earlier
2019-04-17 16:36:03 -07:00
Eddie Hung
709f76c107
Remove use of abc_box_id in stat
2019-04-17 16:35:27 -07:00
Eddie Hung
abcd3103ff
Do not print slack histogram
2019-04-17 15:11:14 -07:00
Eddie Hung
fd89c1056e
Working ABC9 script
2019-04-17 12:33:32 -07:00
Eddie Hung
ae2653c50f
abc9 to output some more info
2019-04-16 16:39:16 -07:00
Eddie Hung
b015ed48f7
Merge remote-tracking branch 'origin/master' into xaig
2019-04-16 15:04:20 -07:00
Eddie Hung
55a3638c71
Port from xc7mux branch
2019-04-16 15:01:45 -07:00
Eddie Hung
fc5fda595d
Merge branch 'xaig' into xc7mux
2019-04-16 13:15:53 -07:00
Eddie Hung
afcb86c3d1
abc9 to call "setundef -zero" behaving as for abc
2019-04-16 13:10:13 -07:00
Eddie Hung
98c297fabf
ABC to read_box before reading netlist
2019-04-16 12:44:10 -07:00
Eddie Hung
b89bb74452
For 'stat' do not count modules with abc_box_id
2019-04-16 11:19:54 -07:00
Eddie Hung
a2b106135b
Do not call abc on modules with abc_box_id attr
2019-04-16 11:19:42 -07:00
Eddie Hung
4da4a6da2f
Revert #895
2019-04-16 11:07:51 -07:00
Eddie Hung
538592067e
Merge branch 'xaig' into xc7mux
2019-04-15 22:04:20 -07:00
Eddie Hung
0391499e46
Merge remote-tracking branch 'origin/master' into xaig
2019-04-15 21:56:45 -07:00
Eddie Hung
b3378745fd
Revert "Recognise default entry in case even if all cases covered (fix for #931 )"
2019-04-15 17:52:45 -07:00
Eddie Hung
9bfcd80063
Handle __dummy_o__ and __const[01]__ in read_aiger not abc
2019-04-12 18:21:16 -07:00
Eddie Hung
482a60825b
abc to ignore __dummy_o__ and __const[01]__ when re-integrating
2019-04-12 18:16:50 -07:00
Eddie Hung
88d43a519b
Use -map instead of -symbols for aiger
2019-04-12 16:29:14 -07:00
Eddie Hung
941365b4bb
Comment out
2019-04-12 12:29:04 -07:00
Eddie Hung
04e466d5e4
Add support for synth_xilinx -abc9 and ignore abc9 -dress opt
2019-04-12 12:28:37 -07:00
Eddie Hung
f77da46a87
Merge remote-tracking branch 'origin/master' into xaig
2019-04-12 12:21:48 -07:00
Eddie Hung
3c1f1a6605
Fix ordering of when to insert zero index
2019-04-11 16:25:59 -07:00
Eddie Hung
53513c52df
Merge remote-tracking branch 'origin/pmux2shiftx' into xc7mux
2019-04-11 16:21:01 -07:00
Eddie Hung
f587950bde
More unused
2019-04-11 16:20:43 -07:00
Eddie Hung
35181a7866
Merge remote-tracking branch 'origin/pmux2shiftx' into xc7mux
2019-04-11 16:18:45 -07:00
Eddie Hung
b15b410b41
Remove unused
2019-04-11 16:18:01 -07:00
Eddie Hung
b1f1db2fcf
Fixes
2019-04-11 16:17:09 -07:00
Eddie Hung
e8c26f2839
WIP
2019-04-11 15:52:04 -07:00
Eddie Hung
09e7eb7aed
Spelling fixes
2019-04-11 15:09:13 -07:00
Eddie Hung
adc6efb584
Recognise default entry in case even if all cases covered ( #931 )
2019-04-11 12:34:51 -07:00
Eddie Hung
5f4024ffd2
Revert "abc -dff now implies "-D 0" otherwise retiming doesn't happen"
...
This reverts commit 19271bd996
.
2019-04-10 08:31:40 -07:00
Eddie Hung
78d35a86c0
Revert ""&nf -D 0" fails => use "-D 1" instead"
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This reverts commit 3c253818ca
.
2019-04-10 08:31:35 -07:00
Eddie Hung
c89cd48f58
Merge remote-tracking branch 'origin/master' into eddie/fix_retime
2019-04-10 08:23:00 -07:00
Eddie Hung
d536379c62
Add "-lut <file>" support to abc9
2019-04-09 14:31:31 -07:00
Eddie Hung
7e304c362b
Add "-box" option to abc9
2019-04-09 10:58:06 -07:00
Eddie Hung
bd523abef5
Add 'setundef -zero' call prior to aigmap in abc9
2019-04-09 10:32:58 -07:00
Eddie Hung
3b6f85b0a6
Comment out
2019-04-09 10:09:43 -07:00
Eddie Hung
3fc474aa73
Add support for synth_xilinx -abc9 and ignore abc9 -dress opt
2019-04-09 10:06:44 -07:00
Eddie Hung
0deaccbaae
Fix a few typos
2019-04-08 16:46:33 -07:00
Eddie Hung
12c34136ba
More space fixing
2019-04-08 16:40:17 -07:00
Eddie Hung
bca3cf6843
Merge branch 'master' into xaig
2019-04-08 16:31:59 -07:00
Eddie Hung
6797f6b6c4
$_XILINX_SHREG_ to preserve src attribute
2019-04-08 16:24:20 -07:00
Eddie Hung
7e773741ab
Merge branch 'undo_pr895' into xc7srl
2019-04-08 16:07:52 -07:00
Eddie Hung
13fc70d7a4
Undo #895 by instead setting an attribute
2019-04-08 16:05:24 -07:00
Eddie Hung
93b1621911
Cope with undoing #895
2019-04-08 15:57:07 -07:00
Eddie Hung
d3930ca79e
Revert "Remove handling for $pmux, since #895"
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This reverts commit aa693d5723
.
2019-04-08 12:01:06 -07:00
David Shah
2bf3ca6443
memory_bram: Fix multiport make_transp
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Signed-off-by: David Shah <dave@ds0.me>
2019-04-07 16:56:31 +01:00
Eddie Hung
1d526b7f06
Call shregmap twice -- once for variable, another for fixed
2019-04-05 17:35:49 -07:00
Eddie Hung
4afcad70e2
Merge branch 'eddie/fix_retime' into xc7srl
2019-04-05 16:30:17 -07:00
Eddie Hung
d559023007
Fix S0 -> S1
2019-04-05 16:28:14 -07:00
Eddie Hung
0364a5d811
Merge branch 'eddie/fix_retime' into xc7srl
2019-04-05 15:46:18 -07:00
Eddie Hung
3c253818ca
"&nf -D 0" fails => use "-D 1" instead
2019-04-05 15:30:19 -07:00
Eddie Hung
19271bd996
abc -dff now implies "-D 0" otherwise retiming doesn't happen
2019-04-05 14:42:25 -07:00
Clifford Wolf
75ca06526a
Added missing argument checking to "mutate" command
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-04 18:10:10 +02:00
Eddie Hung
572603409c
Merge branch 'map_cells_before_map_luts' into xc7srl
2019-04-04 07:54:42 -07:00
Benedikt Tutzer
cae657cebd
Used PyImport_ImportModule instead of PyImport_Import to avoid the explicit conversion to a python string
2019-04-04 10:35:01 +02:00
Benedikt Tutzer
e64b3f1074
Changed filesystem dependency to boost instead of experimental std library
2019-04-04 09:24:50 +02:00
Eddie Hung
aa693d5723
Remove handling for $pmux, since #895
2019-04-03 08:35:32 -07:00
Sylvain Munaut
39380c45ba
proc_mux: Fix crash when trying to optimize non-existant mux to shiftx
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last_mux_cell can be NULL ...
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2019-04-03 14:50:12 +02:00
Benedikt Tutzer
fd7fb1377d
Added cross-platform support for plugin-paths
2019-04-03 13:21:40 +02:00
Eddie Hung
d8465590ac
Merge remote-tracking branch 'origin/master' into xc7srl
2019-04-03 03:36:11 -07:00
Benedikt Tutzer
bbfb43006d
Improved Error reporting when Python passes are loaded
2019-04-03 12:21:56 +02:00
David Shah
6acbc016f4
memory_bram: Consider read enable for address expansion register
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Signed-off-by: David Shah <dave@ds0.me>
2019-04-02 19:47:50 +01:00
Eddie Hung
aaa2690a56
Merge pull request #895 from YosysHQ/pmux2shiftx
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RFC: Add a pmux-to-shiftx optimisation to proc_mux
2019-04-02 00:16:14 -07:00
Benedikt Tutzer
03d1606b42
Merge remote-tracking branch 'origin/master' into feature/python_bindings
2019-03-28 12:16:39 +01:00
Clifford Wolf
32bd0f22ec
Merge pull request #901 from trcwm/libertyfixes
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Libertyfixes: accept superfluous ; at end of group.
2019-03-28 09:32:05 +01:00
Clifford Wolf
662429cc49
Merge pull request #903 from YosysHQ/bram_reset_transp
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memory_bram: Reset make_transp when growing read ports
2019-03-28 09:30:48 +01:00
David Shah
60594ad40c
memory_bram: Reset make_transp when growing read ports
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Signed-off-by: David Shah <dave@ds0.me>
2019-03-27 17:19:14 +00:00
Niels Moseley
263ab60b43
Liberty file parser now accepts superfluous ;
2019-03-27 15:17:58 +01:00
Niels Moseley
487cb45b87
Liberty file parser now accepts superfluous ;
2019-03-27 15:15:53 +01:00
Clifford Wolf
2c7fe42ad1
Add "rename -output"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-27 13:47:42 +01:00
Clifford Wolf
d351b7cb99
Improve "rename" help message
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-27 13:33:26 +01:00
Clifford Wolf
38b3fbd3f0
Add "cutpoint -undef"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-26 16:01:14 +01:00
Clifford Wolf
d0b9b1bece
Add "hdlname" attribute
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-26 14:52:48 +01:00
Eddie Hung
6b90d3cf6c
Merge remote-tracking branch 'origin/master' into xc7srl
2019-03-25 13:17:22 -07:00
Clifford Wolf
ddc1a4488e
Add "cutpoint" pass
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-25 19:49:00 +01:00
Eddie Hung
b7a3d35c6b
Create one $shiftx per bit in width
2019-03-25 11:16:56 -07:00
Clifford Wolf
9ec50ca7b9
Merge pull request #896 from YosysHQ/transp_fixes
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memory_bram: Fix multiclock make_transp
2019-03-25 14:55:16 +01:00
Niels Moseley
1f7f54e68e
spaces -> tabs
2019-03-25 14:12:04 +01:00
Niels Moseley
9d9cc8a314
EOL is now accepted as ';' replacement on lines that look like: feature_xyz(option)
2019-03-25 12:15:10 +01:00
Niels Moseley
3b3b77291a
Updated the liberty parser to accept [A:B] ranges (AST has not been updated). Liberty parser now also accepts key : value pair lines that do not end in ';'.
2019-03-24 22:54:18 +01:00
David Shah
ac6cc88db3
memory_bram: Fix multiclock make_transp
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Signed-off-by: David Shah <dave@ds0.me>
2019-03-24 16:21:36 +00:00
Eddie Hung
2507d01b03
Add a pmux-to-shiftx optimisation to proc_mux
2019-03-23 16:45:36 -07:00
Eddie Hung
bf83c074c8
Cope with SHREG not having E port; Revert $pmux fine tune
2019-03-23 16:09:38 -07:00
Clifford Wolf
ccfa2fe01c
Add "mutate -none -mode", "mutate -mode none"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-23 20:20:32 +01:00
Clifford Wolf
59c44bb61a
Add "mutate -s <filename>"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-23 17:53:09 +01:00
Eddie Hung
098bd5758f
Add support for SHREGMAP+$mux, also fine tune $pmux
2019-03-22 23:22:19 -07:00
Eddie Hung
0895093c7c
Leftover printf
2019-03-22 19:14:04 -07:00
Eddie Hung
456295eb66
Fixes for multibit
2019-03-22 18:32:42 -07:00
Eddie Hung
03d108cd1f
Working for 1 bit
2019-03-22 17:46:49 -07:00
Eddie Hung
46753cf89f
Merge remote-tracking branch 'origin/master' into xc7srl
2019-03-22 13:10:42 -07:00
Clifford Wolf
7cfd83c341
Trim init attributes when resizing FFs in "wreduce", fixes #887
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-22 11:42:19 +01:00
Eddie Hung
5597270b9e
Opt
2019-03-21 10:20:27 -07:00
Eddie Hung
2b911e270b
Fix spacing
2019-03-20 12:28:39 -07:00
Eddie Hung
505e4c2d59
Revert $__SHREG_ to orig; use $__XILINX_SHREG for variable length
2019-03-19 21:58:05 -07:00
Eddie Hung
5445cd4d00
Add support for variable length Xilinx SRL > 128
2019-03-19 17:44:33 -07:00
Eddie Hung
4cd8f02973
shregmap -tech xilinx to delete $shiftx for var length SRL
2019-03-19 15:05:08 -07:00
Eddie Hung
24553326dd
Merge remote-tracking branch 'origin/master' into xc7srl
2019-03-19 13:11:30 -07:00
Eddie Hung
0ea7eba5f1
Make output port a non chain user
2019-03-19 13:08:43 -07:00
Eddie Hung
ed32119d13
Fix shregmap to correctly recognise non chain users; cleanup
2019-03-18 16:12:19 -07:00
Eddie Hung
b94db54664
shiftx NULL pointer check
2019-03-18 13:35:54 -07:00
Eddie Hung
d6d9ef0fee
Cleanup
2019-03-16 12:49:46 -07:00
Eddie Hung
fadeadb8c8
Only accept <128 for variable length, only if $shiftx exclusive
2019-03-16 08:51:13 -07:00
Eddie Hung
06f8f2654a
Working
2019-03-15 19:13:40 -07:00
Clifford Wolf
aa65d3fe65
Improve mix of src/wire/wirebit coverage in "mutate -list"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-16 00:55:46 +01:00
Clifford Wolf
dacaebae35
Add "fmcombine -fwd -bwd -nop"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-15 21:45:37 +01:00
Clifford Wolf
370db33a4c
Add fmcombine pass
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-15 20:46:17 +01:00
Clifford Wolf
d1985f6a22
Improvements in "mutate" list-reduce algorithm
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-15 00:18:31 +01:00
Clifford Wolf
27a5d9c91e
Add "mutate -cfg", improve pick_cover behavior
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-14 23:20:41 +01:00
Clifford Wolf
4d304e3da7
Add a strictly coverage-driven mutation selection strategy
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-14 23:01:55 +01:00
Clifford Wolf
2a4263a75d
Improve "mutate" wire coverage metric
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-14 23:01:01 +01:00
Clifford Wolf
1b4fdbb0d8
Add more mutation types, improve mutation src cover
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-14 22:04:42 +01:00
Clifford Wolf
6ad5d036c5
Add "mutate" command DB reduce functionality
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-14 22:04:42 +01:00
Clifford Wolf
8e6b69d7bb
Add "mutate -mode inv", various other mutate improvements
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-14 22:04:42 +01:00
Clifford Wolf
ea8ee24140
Add basic "mutate -list N" framework
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-14 22:04:42 +01:00
Clifford Wolf
f806b95ed6
Improve handling of and-with-1 and or-with-0 in opt_expr, fixes #327
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-14 20:52:00 +01:00
Eddie Hung
8af9979aab
Revert "Add shregmap -init_msb_first and use in synth_xilinx"
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This reverts commit 26ecbc1aee
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2019-03-14 09:01:48 -07:00
Eddie Hung
f1a8e8a480
Merge remote-tracking branch 'origin/master' into xc7srl
2019-03-14 08:59:19 -07:00
Eddie Hung
26ecbc1aee
Add shregmap -init_msb_first and use in synth_xilinx
2019-03-14 08:10:02 -07:00
Clifford Wolf
399ab16315
Add $dffsr support to async2sync
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-09 11:52:00 -08:00
Eddie Hung
d03780c3f4
Fix spelling in pmgen/README.md
2019-03-05 17:55:29 -08:00
Clifford Wolf
ae9286386d
Only run derive on blackbox modules when ports have dynamic size
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-02 12:36:46 -08:00
Larry Doolittle
57f8bb471f
Try again for passes/pmgen/ice40_dsp_pm.h rule
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Tested on both in-tree and out-of-tree builds
2019-03-01 20:20:53 -08:00
Clifford Wolf
e847690bda
Fix multiple issues in wreduce FF handling, fixes #835
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-28 17:24:46 -08:00
Larry Doolittle
e2fc18f27b
Reduce amount of trailing whitespace in code base
2019-02-28 14:58:11 -08:00
Clifford Wolf
68a6937173
Fix pmgen for in-tree builds
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-28 14:56:05 -08:00
Clifford Wolf
64d91219b4
Fix pmgen for out-of-tree build
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-28 14:00:58 -08:00
Clifford Wolf
63be3f3bab
Improvements in "supercover" pass
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-27 11:45:13 -08:00
Clifford Wolf
a58dbcf2ba
Add "supercover" skeleton
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-27 11:37:08 -08:00
Eddie Hung
f7c7003a19
Merge remote-tracking branch 'origin/master' into xaig
2019-02-26 13:16:03 -08:00
Eddie Hung
7cac3b1c8b
abc9 -- multiple connections for inouts
2019-02-26 12:18:28 -08:00
Larry Doolittle
61fc411c5d
Clean up some whitepsace outliers
2019-02-26 09:39:46 -08:00
Eddie Hung
967297cd57
abc9 cleanup
2019-02-25 18:40:53 -08:00
Eddie Hung
721f6a14fb
read_aiger to accept empty string for clk_name, passable only if no latches
2019-02-25 15:34:02 -08:00
Eddie Hung
0ca3fd6a1c
abc9 not to clean after aigmap
2019-02-25 15:31:52 -08:00
Eddie Hung
51f28a6747
abc9 to call "clean" once at the end of all abc9_module() calls
2019-02-25 12:55:47 -08:00
Clifford Wolf
c258b99040
Minor changes ontop of 71bcc4c: Remove hierarchy warning that is redundant to -check
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-24 20:41:36 +01:00
Clifford Wolf
c118f9a377
Merge pull request #812 from ucb-bar/arrayhierarchyfixes
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Define basic_cell_type() function and use it to derive the cell type …
2019-02-24 11:39:13 -08:00
Clifford Wolf
cd722f26a5
Cleanups in ARST handling in wreduce
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-24 20:34:23 +01:00
Clifford Wolf
da14bc8524
Merge pull request #824 from litghost/fix_reduce_on_ff
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Fix WREDUCE on FF not fixing ARST_VALUE parameter.
2019-02-24 11:29:14 -08:00
Jim Lawson
71bcc4c644
Address requested changes - don't require non-$ name.
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Suppress warning if name does begin with a `$`.
Fix hierachy tests so they have something to grep.
Announce hierarchy test types.
2019-02-22 16:06:10 -08:00
Keith Rothman
25680f6a07
Fix WREDUCE on FF not fixing ARST_VALUE parameter.
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Adds test case that fails without code change.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-02-22 10:30:42 -08:00
Eddie Hung
d56f02d1fc
abc9 to use AIGER symbol table, as opposed to map file
2019-02-21 17:03:40 -08:00
Clifford Wolf
344afdcd5f
Merge pull request #740 from daveshah1/improve_dress
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Improve ABC netname preservation
2019-02-22 01:16:34 +01:00
Eddie Hung
2811d66dea
Revert "abc9 to write_xaiger -symbols, not -map"
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This reverts commit 04429f8152
.
2019-02-21 14:58:40 -08:00
Eddie Hung
7ad9628f07
Remove irrelevant citations
2019-02-21 14:41:11 -08:00
Eddie Hung
085ed9f487
Add attribution
2019-02-21 14:40:13 -08:00
Eddie Hung
875a02a6f2
abc9 to not select anything extra, and pop selection after final clean
2019-02-21 14:38:52 -08:00
Eddie Hung
04429f8152
abc9 to write_xaiger -symbols, not -map
2019-02-21 14:28:36 -08:00
Eddie Hung
3307295488
Merge branch 'read_aiger' into xaig
2019-02-21 14:27:32 -08:00
Eddie Hung
7f8f36273a
abc9 to use &mfs
2019-02-21 13:16:24 -08:00
Eddie Hung
a8803a1519
Merge remote-tracking branch 'origin/master' into xaig
2019-02-21 11:23:00 -08:00
Eddie Hung
6b96df41bc
abc9 to only disconnect output ports of AND and NOT gates
2019-02-21 11:15:47 -08:00
Clifford Wolf
d55790909c
Hotfix for 4c82ddf
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-21 19:27:23 +01:00
Keith Rothman
4c82ddf394
Add -params mode to force undef parameters in selected cells.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-02-21 10:16:38 -08:00
Clifford Wolf
0e371109b0
Merge pull request #818 from YosysHQ/clifford/dffsrfix
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Fix opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_, fixes #816
2019-02-21 18:58:44 +01:00
Clifford Wolf
893194689d
Fix typo in passes/pmgen/README.md
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-21 18:50:02 +01:00
Eddie Hung
be061810d7
Merge branch 'clifford/dffsrfix' of https://github.com/YosysHQ/yosys into xaig
2019-02-21 09:31:17 -08:00
Clifford Wolf
2da4c9c8f0
Fix opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_, fixes #816
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-21 13:49:45 +01:00
Clifford Wolf
2fe1c830eb
Bugfix in ice40_dsp
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-21 13:28:46 +01:00
Eddie Hung
7f26043caf
ABC -> ABC9
2019-02-20 17:36:57 -08:00
Eddie Hung
e5b8bb9faa
abc9 to disconnect mapped_mods POs correctly, and do not count $_NOT_
2019-02-20 17:33:35 -08:00
Eddie Hung
32853b1f8d
lut/not/and suffix to be ${lut,not,and}
2019-02-20 16:30:30 -08:00
Eddie Hung
2ca83005fb
abc9 to cope with multiple modules
2019-02-20 12:56:15 -08:00
Eddie Hung
d6b317b349
abc9 to use & syntax for -fast, and name fixes
2019-02-20 12:40:17 -08:00
Clifford Wolf
218e9051bb
Add "synth_ice40 -dsp"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-20 16:42:27 +01:00
Clifford Wolf
246391200e
Add FF support to wreduce
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-20 16:36:42 +01:00
Clifford Wolf
dca65d83a0
Detect and reject cases that do not map well to iCE40 DSPs (yet)
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-20 11:18:19 +01:00
Eddie Hung
62e5ff9ba8
abc9 to cope with indexed wires when creating $lut from $_NOT_
2019-02-19 16:06:03 -08:00
Jim Lawson
5c4a72c43e
Fix normal (non-array) hierarchy -auto-top.
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Add simple test.
2019-02-19 14:35:15 -08:00
Eddie Hung
8158bc3f99
abc9 to replace $_NOT_ with $lut
2019-02-19 12:30:20 -08:00
Clifford Wolf
5a853ed46c
Add actual DSP inference to ice40_dsp pass
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-17 15:35:48 +01:00
Clifford Wolf
c06c062469
Merge branch 'master' of github.com:YosysHQ/yosys into pmgen
2019-02-17 12:10:19 +01:00
Eddie Hung
45d49d5d14
Get rid of debugging stuff in abc9
2019-02-16 22:25:22 -08:00
Eddie Hung
f853b2f3c1
abc9 to write_aiger with -O option, and ignore dummy outputs
2019-02-16 20:09:40 -08:00
Eddie Hung
d8c4d4e6c7
abc9 to handle comb loops, cope with constant outputs, disconnect using new wire
2019-02-16 13:47:38 -08:00
Eddie Hung
e7c7ab8fc0
expose command to not skip 'internal' wires beginning with '$'
2019-02-16 13:45:17 -08:00
Eddie Hung
d4545d415b
abc9 to cope with non-wideports, count cells properly
2019-02-16 08:53:06 -08:00
Eddie Hung
f8d0134598
Move lookup inside if
2019-02-15 15:23:26 -08:00
Eddie Hung
a786ac4d53
Refactor
2019-02-15 13:00:13 -08:00
Eddie Hung
914546efd9
Cope with width != 1 when re-mapping cells
2019-02-15 12:55:52 -08:00
Eddie Hung
956ee545c5
abc9 to stitch results with CI/CO properly
2019-02-15 11:52:34 -08:00
Jim Lawson
5c504c5ae6
Define basic_cell_type() function and use it to derive the cell type for array references (instead of duplicating the code).
2019-02-15 11:31:37 -08:00
Eddie Hung
206f11dca3
Fix stitching
2019-02-13 17:04:23 -08:00
Eddie Hung
f0f5d8a5cc
Merge remote-tracking branch 'origin/read_aiger' into xaig
2019-02-13 14:09:36 -08:00
Eddie Hung
06cf0555ee
Merge https://github.com/YosysHQ/yosys into xaig
2019-02-13 14:08:31 -08:00
Eddie Hung
87f059adf7
Rip out some more stuff
2019-02-13 10:44:52 -08:00
Eddie Hung
045f7763ae
Rip out unused functions in abc9
2019-02-12 16:25:22 -08:00
Eddie Hung
b3341b4abb
WIP for ABC with aiger
2019-02-12 09:31:22 -08:00
Eddie Hung
c23e3f0751
Missing headers for Xcode?
2019-02-12 09:24:13 -08:00
Eddie Hung
5a0a5aae4f
Compile abc9
2019-02-08 13:58:47 -08:00
Eddie Hung
e25a22015f
Copy abc.cc to abc9.cc
2019-02-08 13:23:54 -08:00
David Shah
a4515712cb
fsm_opt: Fix runtime error for FSMs without a reset state
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Signed-off-by: David Shah <dave@ds0.me>
2019-02-07 10:35:36 +00:00
David Shah
58c22dae31
abc: Improved recovered netnames, also preserve src on nets with dress
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Signed-off-by: David Shah <davey1576@gmail.com>
2019-02-06 22:23:13 +01:00
David Shah
8524a479b1
abc: Preserve naming through ABC using 'dress' command
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Signed-off-by: David Shah <dave@ds0.me>
2019-02-06 22:23:13 +01:00
whitequark
58d059ccb7
proc_clean: fix critical typo.
2019-01-23 22:08:38 +00:00
whitequark
95b6c35882
proc_clean: fix fully def check to consider compare/signal length.
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Fixes #790 .
2019-01-18 23:22:19 +00:00
Clifford Wolf
8ddec5d882
Progress in pmgen
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-01-15 11:23:25 +01:00
Clifford Wolf
5216735210
Progress in pmgen, add pmgen README
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-01-15 11:23:25 +01:00
Clifford Wolf
55ac030382
Fix pmgen "reject" statement
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-01-15 11:23:25 +01:00
Clifford Wolf
d45379936b
Progress in pmgen
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-01-15 11:23:25 +01:00
Clifford Wolf
1f8e76f993
Progress in pmgen
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-01-15 11:23:25 +01:00
Clifford Wolf
b9545aa0e1
Progress in pmgen
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-01-15 11:23:25 +01:00
Clifford Wolf
ad69c668ce
Add mockup .pmg (pattern matcher generator) file
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-01-15 11:23:25 +01:00
whitequark
e792bd56b7
flowmap: clean up terminology.
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* "map": group gates into LUTs;
* "pack": replace gates with LUTs.
This is important because we have FlowMap and DF-Map, and currently
our messages are ambiguous.
Also clean up some other log messages while we're at it.
2019-01-08 02:05:06 +00:00
whitequark
211c26a4c9
flowmap: implement depth relaxation.
2019-01-08 01:13:05 +00:00
Clifford Wolf
8a63fc51d3
Bugfix in $memrd sharing
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-01-07 10:04:47 +01:00
Clifford Wolf
dbd51d7bda
Merge pull request #782 from whitequark/flowmap_dfs
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flowmap: construct a max-volume max-flow min-cut, not just any one
2019-01-07 09:47:57 +01:00
Clifford Wolf
b5f6e786ea
Switch "bugpoint" from system() to run_command()
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-01-07 09:45:21 +01:00
whitequark
a342d6db49
bugpoint: new pass.
...
A typical use of `bugpoint` would involve a script with a pass under
test, e.g.:
flowmap -relax -optarea 100
and would be invoked as:
bugpoint -yosys ./yosys -script flowmap.ys -clean -cells
This replaces the current design with the minimal design that still
crashes the `flowmap.ys` script.
`bugpoint` can also be used to perform generic design minimization
using `select`, e.g. the following script:
select i:* %x t:$_MUX_ %i -assert-max 0
would remove all parts of the design except for an unbroken path from
an input to an output port that goes through exactly one $_MUX_ cell.
(The condition is inverted.)
2019-01-07 03:13:19 +00:00
whitequark
8b44198e23
flowmap: construct a max-volume max-flow min-cut, not just any one.
2019-01-06 19:51:37 +00:00
Scott Mansell
62c90c4e17
Rename cells based on the wires they drive.
2019-01-06 19:00:16 +13:00
whitequark
2fcc1ee72e
flowmap: add -minlut option, to allow postprocessing with opt_lut.
2019-01-04 21:18:03 +00:00
whitequark
9bc5cf0844
flowmap: cleanup for clarity. NFCI.
2019-01-04 13:04:20 +00:00
whitequark
fd21564deb
flowmap: improve debug graph output. NFC.
2019-01-04 03:30:04 +00:00
whitequark
7850a0c28a
flowmap: add link to longer version of paper. NFC.
2019-01-04 02:33:10 +00:00
Clifford Wolf
d98fe8ce1f
Merge pull request #775 from whitequark/opt_flowmap
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flowmap: new techmap pass
2019-01-03 17:03:18 +01:00
whitequark
07af772a72
flowmap: new techmap pass.
2019-01-03 14:28:19 +00:00
Clifford Wolf
0fc6e2bfcf
Merge pull request #770 from whitequark/opt_expr_cmp
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opt_expr: refactor and improve simplification of comparisons
2019-01-02 17:34:04 +01:00
whitequark
bf8db55ef3
opt_expr: improve simplification of comparisons with large constants.
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The idea behind this simplification is that a N-bit signal X being
compared with an M-bit constant where M>N and the constant has Nth
or higher bit set, it either always succeeds or always fails.
However, the existing implementation only worked with one-hot signals
for some reason. It also printed incorrect messages.
This commit adjusts the simplification to have as much power as
possible, and fixes other bugs.
2019-01-02 15:45:28 +00:00
Clifford Wolf
979de95cf6
Merge pull request #750 from Icenowy/anlogic-ff-init
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Initialization of Anlogic DFFs
2019-01-02 15:52:22 +01:00
Clifford Wolf
2e606b1802
Merge pull request #773 from whitequark/opt_lut_elim_fixes
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opt_lut: elimination fixes
2019-01-02 15:45:29 +01:00
whitequark
efa278e232
Fix typographical and grammatical errors and inconsistencies.
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The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.
DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint
More hits were found by looking through comments and strings manually.
2019-01-02 13:12:17 +00:00
whitequark
c55dfb8369
opt_lut: reflect changes in sigmap.
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Otherwise, some LUTs will be missed during elimination.
2019-01-02 10:21:58 +00:00
whitequark
06143ab33f
opt_lut: use a worklist, and revisit cells affected by elimination.
2019-01-02 09:36:32 +00:00
whitequark
f7363ac508
opt_lut: count eliminated cells, and set opt.did_something for them.
2019-01-02 09:14:43 +00:00
whitequark
4fd458290c
opt_expr: refactor simplification of unsigned X<onehot and X>=onehot. NFCI.
2019-01-02 05:11:29 +00:00
whitequark
9e9846a6ea
opt_expr: refactor simplification of signed X>=0 and X<0. NFCI.
2019-01-02 03:01:25 +00:00
whitequark
8e53d2e0bf
opt_expr: simplify any unsigned comparisons with all-0 and all-1.
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Before this commit, only unsigned comparisons with all-0 would be
simplified. This commit also makes the code handling such comparisons
to be more rigorous and not abort on unexpected input.
2019-01-02 02:45:49 +00:00
whitequark
42c356c49c
opt_lut: eliminate LUTs evaluating to constants or inputs.
2018-12-31 23:55:40 +00:00
Clifford Wolf
0a840dd883
Fix handling of (* keep *) wires in wreduce
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-31 16:37:40 +01:00
whitequark
18291c20d2
proc_clean: remove any empty cases if all cases use all-def compare.
2018-12-23 09:04:30 +00:00
whitequark
b784440857
proc_clean: remove any empty cases at the end of the switch.
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Previously, only completely empty switches were removed.
2018-12-22 09:04:46 +00:00
whitequark
0c318e7db5
memory_collect: do not truncate 'x from \INIT.
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The semantics of an RTLIL constant that has less bits than its
declared bit width is zero padding. Therefore, if the output of
memory_collect will be used for simulation, truncating 'x from
the end of \INIT will produce incorrect simulation results.
2018-12-21 02:01:27 +00:00
David Shah
2b16d4ed3d
memory_dff: Fix typo when checking init value
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-12-18 17:40:01 +00:00
Icenowy Zheng
256fb8c95c
Add "dffinit -noreinit" parameter
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Sometimes the FF cell might be initialized during the map process, e.g.
some FPGA platforms (Anlogic Eagle and Lattice ECP5 for example) has
only a "SR" pin for a FF for async reset, that resets the FF to the
initial value, which means the async reset value should be set as the
initial value. In this case the DFFINIT pass shouldn't reinitialize it
to a different value, which will lead to error.
Add a "-noreinit" parameter for the safeguard. If a FF is not
technically initialized before DFFINIT pass, the default value should be
set to x.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-12-18 23:10:40 +08:00
Icenowy Zheng
fec8b3c81f
Add "dffinit -strinit high low"
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On some platforms the string to initialize DFF might not be "high" and
"low", e.g. with Anlogic TD it's "SET" and "RESET".
Add a "-strinit" parameter for dffinit to allow specify the strings used
for high and low.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-12-18 15:37:43 +08:00
Clifford Wolf
2641a3089b
Revert "Proof-of-concept: preserve naming through ABC using dress"
2018-12-16 21:27:31 +01:00
Clifford Wolf
ddff75b60a
Merge pull request #736 from whitequark/select_assert_list
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select: print selection if a -assert-* flag causes an error
2018-12-16 16:45:49 +01:00
whitequark
f6412d7109
select: print selection if a -assert-* flag causes an error.
2018-12-16 15:44:29 +00:00
Clifford Wolf
0d9c850a07
Merge pull request #735 from daveshah1/trifixes
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deminout fixes
2018-12-16 16:02:21 +01:00
Clifford Wolf
f53e19cc71
Fix equiv_opt indenting
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-16 15:57:28 +01:00
Clifford Wolf
2a681909df
Merge pull request #724 from whitequark/equiv_opt
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equiv_opt: new command, for verifying optimization passes
2018-12-16 15:54:26 +01:00
Clifford Wolf
a2154c1be0
Merge pull request #734 from grahamedgecombe/fix-shuffled-bram-initdata
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memory_bram: Fix initdata bit order after shuffling
2018-12-16 15:53:44 +01:00
Clifford Wolf
a1fb5b1e4b
Merge pull request #714 from daveshah1/abc_preserve_naming
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Proof-of-concept: preserve naming through ABC using dress
2018-12-16 15:41:30 +01:00
Clifford Wolf
19ca4e2ac3
Merge pull request #722 from whitequark/rename_src
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rename: add -src, for inferring names from source locations
2018-12-16 15:28:29 +01:00
Clifford Wolf
556341a77f
Merge pull request #720 from whitequark/master
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lut2mux: handle 1-bit INIT constant in $lut cells
2018-12-16 15:27:23 +01:00
David Shah
4c59447168
deminout: Consider $tribuf cells
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Signed-off-by: David Shah <dave@ds0.me>
2018-12-12 17:17:40 +00:00
David Shah
d3fe9465f3
deminout: Don't demote constant-driven inouts to inputs
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Signed-off-by: David Shah <dave@ds0.me>
2018-12-12 16:50:46 +00:00
Graham Edgecombe
4fef9689ab
memory_bram: Fix initdata bit order after shuffling
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In some cases the memory_bram pass shuffles the order of the bits in a
memory's RD_DATA port. Although the order of the bits in the WR_DATA and
WR_EN ports is changed to match the RD_DATA port, the order of the bits
in the initialization data is not.
This causes reads of initialized memories to return invalid data (until
the initialization data is overwritten).
This commit fixes the bug by shuffling the initdata bits in exactly the
same order as the RD_DATA/WR_DATA/WR_EN bits.
2018-12-11 21:02:49 +00:00
whitequark
7ff5a9db2d
equiv_opt: pass -D EQUIV when techmapping.
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This allows avoiding techmap crashes e.g. because of large memories
in white-box cell models.
2018-12-07 17:20:34 +00:00
whitequark
c38ea9ae65
equiv_opt: new command, for verifying optimization passes.
2018-12-07 17:20:34 +00:00
whitequark
7ec740b7ad
opt_lut: leave intact LUTs with cascade feeding module outputs.
2018-12-07 17:13:52 +00:00
whitequark
9eb03d458d
opt_lut: show original truth table for both cells.
2018-12-07 17:04:41 +00:00
whitequark
a8ab722824
opt_lut: add -limit option, for debugging misoptimizations.
2018-12-07 16:36:26 +00:00
David Shah
1dfb2fecab
abc: Preserve naming through ABC using 'dress' command
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Signed-off-by: David Shah <dave@ds0.me>
2018-12-06 15:05:07 +00:00
Clifford Wolf
643f858acf
Bugfix in opt_expr handling of a<0 and a>=0
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-06 07:29:21 +01:00
whitequark
a9baee4b24
rename: add -src, for inferring names from source locations.
2018-12-05 20:35:13 +00:00
whitequark
d1f2cb01dc
lut2mux: handle 1-bit INIT constant in $lut cells.
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This pass already handles INIT constants shorter than 2^width, but
that was not done for the recursion base case.
2018-12-05 19:27:48 +00:00
whitequark
88217d0157
opt_lut: simplify type conversion. NFC.
2018-12-05 19:12:02 +00:00
Clifford Wolf
2d98db73e3
Rename opt_lut.cpp to opt_lut.cc
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-05 18:03:58 +01:00
whitequark
45cb6200af
opt_lut: add -dlogic, to avoid disturbing logic such as carry chains.
2018-12-05 16:30:37 +00:00
whitequark
e603484070
opt_lut: always prefer to eliminate 1-LUTs.
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These are always either buffers or inverters, and keeping the larger
LUT preserves more source-level information about the design.
2018-12-05 16:30:37 +00:00
whitequark
59eea0183f
opt_lut: collect and display statistics.
2018-12-05 16:30:37 +00:00
whitequark
e54c7e951c
opt_lut: refactor to use a worker. NFC.
2018-12-05 16:30:37 +00:00
whitequark
9e072ec21f
opt_lut: new pass, to combine LUTs for tighter packing.
2018-12-05 16:30:37 +00:00
Clifford Wolf
c800e3bb16
Fix typo
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-04 23:30:23 +01:00
Clifford Wolf
70c417174d
Merge pull request #702 from smunaut/min_ce_use
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Add option to only use DFFE is the resulting E signal would be use > N times
2018-12-04 14:29:21 -08:00
Clifford Wolf
47c89d600c
Merge pull request #676 from rafaeltp/master
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Splits SigSpec into bits before calling check_signal_in_fanout (solves #675 )
2018-12-01 04:11:19 +01:00
Sylvain Munaut
8d3ab626ea
dff2dffe: Add option for unmap to only remove DFFE with low CE signal use
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Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-27 21:50:42 +01:00
Clifford Wolf
ab97eddee9
Add iteration limit to "opt_muxtree"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-11-20 17:56:47 +01:00
Niels Moseley
cfc9b9147c
DFFLIBMAP: changed 'missing pin' error into a warning with additional reason/info.
2018-11-06 12:11:52 +01:00
Clifford Wolf
719e29404a
Allow square brackets in liberty identifiers
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-11-05 12:33:33 +01:00
Niels Moseley
04cd179696
Liberty file newline handling is more relaxed. More descriptive error message
2018-11-03 18:38:49 +01:00
Niels Moseley
d1e8249f9a
Report an error when a liberty file contains pin references that reference non-existing pins
2018-11-03 18:07:51 +01:00
rafaeltp
f8b97e21f3
using [i] to access individual bits of SigSpec and merging bits into a tmp Sig before setting the port to new signal
2018-10-21 11:32:44 -07:00
rafaeltp
7b964bfb83
cleaning up for PR
2018-10-20 18:02:59 -07:00
rafaeltp
ce069830c5
fixing code style
2018-10-20 17:57:26 -07:00
rafaeltp
0ad4321781
solves #675
2018-10-20 17:50:21 -07:00
Ruben Undheim
436e3c0a7c
Refactor code to avoid code duplication + added comments
2018-10-20 16:06:48 +02:00
Ruben Undheim
397dfccb30
Support for SystemVerilog interfaces as a port in the top level module + test case
2018-10-20 11:58:25 +02:00
Clifford Wolf
6514443a5c
Merge pull request #672 from daveshah1/fix_bram
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memory_bram: Reset make_outreg when growing read ports
2018-10-19 16:09:11 +02:00
David Shah
3420ae5ca5
memory_bram: Reset make_outreg when growing read ports
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Signed-off-by: David Shah <dave@ds0.me>
2018-10-19 14:46:31 +01:00
Clifford Wolf
f24bc1ed0a
Merge pull request #659 from rubund/sv_interfaces
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Support for SystemVerilog interfaces and modports
2018-10-18 10:58:47 +02:00
Ruben Undheim
c50afc4246
Documentation improvements etc.
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- Mention new feature in the SystemVerilog section in the README file
- Commented changes much better
- Rename a few signals to make it clearer
- Prevent warning for unused signals in an easier way
- Add myself as copyright holder to 2 files
- Fix one potential memory leak (delete 'wire' if not in modport)
2018-10-13 20:34:44 +02:00
tklam
f4343b3dc7
stop check_signal_in_fanout from traversing FFs
2018-10-13 23:24:24 +08:00
tklam
302edf0429
stop check_signal_in_fanout from traversing FFs
2018-10-13 23:11:19 +08:00
Ruben Undheim
458a94059e
Support for 'modports' for System Verilog interfaces
2018-10-12 21:11:48 +02:00
Ruben Undheim
75009ada3c
Synthesis support for SystemVerilog interfaces
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This time doing the changes mostly in AST before RTLIL generation
2018-10-12 21:11:36 +02:00
tklam
b86eb3deef
fix bug: pass by reference
2018-09-26 17:57:39 +08:00
TK Lam
2b89074240
Fix issue #639
2018-09-26 16:11:45 +08:00
Clifford Wolf
592a82c0ad
Merge pull request #625 from aman-goel/master
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Minor revision to -expose in setundef pass
2018-09-14 12:36:13 +02:00
acw1251
5fe16c25b8
Fixed minor typo in "sim" help message
2018-09-12 18:34:27 -04:00
Aman Goel
75c1f8d241
Minor revision to -expose in setundef pass
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Adds default value option as -undef when -expose used. Not having set the value mode set can cause the setundef pass to abort.
2018-09-10 21:44:36 -04:00
Benedikt Tutzer
95d65971f3
added some checks if python is enabled to make sure everything compiles if python is disabled in the makefile
2018-08-20 16:04:43 +02:00
Benedikt Tutzer
d87c7df27f
Two passes are not allowed to have the same filename
2018-08-20 15:28:09 +02:00
Benedikt Tutzer
6d18837d62
Python passes are now looked for in share/plugins and can be added by specifying a relative or absolute path
2018-08-20 15:11:06 +02:00
Clifford Wolf
05466790a6
Merge pull request #606 from cr1901/show-win
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`show` pass `-format` and `-viewer` improvements on Windows
2018-08-19 15:25:46 +02:00
Aman Goel
83b41260f6
Revision to expose option in setundef pass
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Corrects indentation
Simplifications and corrections
2018-08-18 09:08:07 +05:30
Aman Goel
61f002c908
Merge pull request #3 from YosysHQ/master
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Updates from official repo
2018-08-18 08:18:40 +05:30
Benedikt Tutzer
d79a2808cf
Python Passes can now be added with the -m option or with the plugin command. There are still issues when run in shell mode, but they can be used just fine in a python script
2018-08-16 16:00:11 +02:00
William D. Jones
7ce7ea2eb4
Update show pass documentation with Windows caveats.
2018-08-15 17:18:19 -04:00
William D. Jones
9f91c62348
Fix run_command() when using -format and -viewer in show pass.
2018-08-15 17:18:19 -04:00
Clifford Wolf
67b1026297
Merge pull request #591 from hzeller/virtual-override
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Consistent use of 'override' for virtual methods in derived classes.
2018-08-15 14:05:38 +02:00
Clifford Wolf
0eaab6cd1d
Add missing <deque> include (MSVC build fix)
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-07-22 15:21:59 +02:00
Henner Zeller
3aa4484a3c
Consistent use of 'override' for virtual methods in derived classes.
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o Not all derived methods were marked 'override', but it is a great
feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
use the plain keyword going forward now that C++11 is established)
2018-07-20 23:51:06 -07:00
Clifford Wolf
87aef8f0cc
Add async2sync pass
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-07-19 15:31:12 +02:00
Aman Goel
5dcb899e76
Merge pull request #2 from YosysHQ/master
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Merging with official repo
2018-07-18 11:34:18 -04:00
David Shah
459d367913
ecp5: Adding synchronous set/reset support
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-14 16:18:01 +02:00
Aman Goel
4d343fc1cd
Merging with official repo
2018-07-04 15:14:28 -04:00
Clifford Wolf
5f2bc1ce76
Add automatic verific import in hierarchy command
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-20 23:45:01 +02:00
Clifford Wolf
675a44b41a
Be slightly less aggressive in "deminout" pass
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-19 14:29:38 +02:00
Edmond Cote
d89560a0ba
Include module name for area summary stats
...
The PR prints the name of the module when displaying the final area count.
Pros:
- Easier for the user to `grep` for area information about a specific module
Cons:
- Arguably more verbose, less "pretty" than author desires
Verification:
~~~~
30c30
< Chip area for this module: 20616.349000
---
> Chip area for module '$paramod$d1738fc0bb353d517bc2caf8fef2abb20bced034\picorv32': 20616.349000
70c70
< Chip area for this module: 88.697700
---
> Chip area for module '\picorv32_axi_adapter': 88.697700
102c102
< Chip area for this module: 20705.046700
---
> Chip area for top module '\picorv32_axi': 20705.046700
~~~~
2018-06-18 17:29:01 -07:00
Clifford Wolf
f273291dfe
Add setundef -anyseq / -anyconst support to -undriven mode
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-01 11:57:28 +02:00
Clifford Wolf
4cd6d5556a
Add "setundef -anyconst"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-01 11:49:58 +02:00
Clifford Wolf
3ab79a231b
Bugfix in handling of array instances with empty ports
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-31 18:09:31 +02:00
Clifford Wolf
cee4b1e6bc
Disable memory_dff for initialized FFs
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-28 17:16:15 +02:00
Clifford Wolf
74efafc1cf
Add some cleanup code to memory_nordff
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-28 16:42:06 +02:00
Robert Ou
9763e4d830
Fix infinite loop in abc command under emscripten
2018-05-18 22:42:39 -07:00
Robert Ou
bfce3a7479
Add an option to statically link abc into yosys
...
This is currently incomplete because the output filter no longer works.
2018-05-18 22:35:28 -07:00
Aman Goel
6e63df6dd0
Correction to -expose with setundef
2018-05-15 13:06:23 -04:00
Clifford Wolf
fe80b39f56
Fix iopadmap for loops between tristate IO buffers
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-15 14:02:27 +02:00
Clifford Wolf
edd297fb1c
Fix iopadmap for cases where IO pins already have buffers on them
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-15 13:13:43 +02:00
Aman Goel
8b9a8c7f91
Minor correction
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Minor typo error correction in -expose with setundef
2018-05-14 18:58:49 -04:00
Aman Goel
b4a303a1b7
Corrections to option -expose in setundef pass
2018-05-13 20:13:54 -04:00
Aman Goel
9286acb687
Add option -expose to setundef pass
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Option -expose converts undriven wires to inputs.
Example usage: setundef -undriven -expose [selection]
2018-05-13 16:53:35 -04:00
Clifford Wolf
0fad1570b5
Some cleanups in setundef.cc
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-13 16:36:12 +02:00
Christian Krämer
c1ecb1b2f1
Add "#ifdef __FreeBSD__"
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(Re-commit e3575a8
with corrected author field)
2018-05-13 13:08:26 +02:00
Clifford Wolf
1167538d26
Revert "Add "#ifdef __FreeBSD__""
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This reverts commit e3575a86c5
.
2018-05-13 13:06:36 +02:00
Clifford Wolf
587056447e
Add optimization of tristate buffer with constant control input
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-12 15:18:27 +02:00
Clifford Wolf
11406a8082
Add "hierarchy -simcheck"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-12 13:59:13 +02:00
Johnny Sorocil
e3575a86c5
Add "#ifdef __FreeBSD__"
2018-05-05 13:02:44 +02:00
Clifford Wolf
145c685de0
Add ABC FAQ to "help abc"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-04 21:59:31 +02:00
Clifford Wolf
a572b49538
Replace -ignore_redef with -[no]overwrite
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-03 15:25:59 +02:00
Clifford Wolf
705c366a91
Added missing dont_use handling for SR FFs to dfflibmap
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-04-05 11:01:45 +02:00
Clifford Wolf
665eec3d53
Removed $timescale from "sat" command VCD writer
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-29 12:38:41 +02:00
Clifford Wolf
ee3c12d6d9
Chenged "extensions_map" to "extensions_list" in hierarchy.cc
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-27 14:12:57 +02:00
Sergi Granell
f93f8aaa11
passes/hierarchy: Reduce code duplication in expand_module
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This also makes it easier to add new file extensions support.
Signed-off-by: Sergi Granell <xerpi.g.12@gmail.com>
2018-03-27 09:35:20 +02:00
Clifford Wolf
491c352da7
Add .sv support to "hierarchy -libdir"
2018-03-26 21:19:00 +02:00
Clifford Wolf
08225f49a4
Add "expose -input"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-12 13:52:52 +01:00
Clifford Wolf
83ffb23739
Add "setundef -undef"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-12 13:52:35 +01:00
Clifford Wolf
a74f805ba0
Fix handling of src attributes in flatten
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-10 13:55:30 +01:00
Clifford Wolf
73c01dca65
Add "memory_nordff" pass
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-06 23:31:51 +01:00
Clifford Wolf
61a9e2eeb3
Fix connwrappers help message
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-04 22:54:34 +01:00
Clifford Wolf
d31584c649
Add $dlatchsr support to clk2fflogic
2018-02-26 12:20:28 +01:00
Clifford Wolf
fba499b866
Fix opt_rmdff handling of $dlatchsr
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-02-26 11:46:05 +01:00
Clifford Wolf
eb67a7532b
Add $allconst and $allseq cell types
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-02-23 13:14:47 +01:00
Clifford Wolf
717abc93a8
Recognize stand-alone obj pattern even when it contains a slash
2018-02-13 14:55:24 +01:00
Clifford Wolf
9337e4999d
Improve log messages in equiv_make
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-01-19 16:20:40 +01:00
Clifford Wolf
9ac560f5d3
Add "dffinit -highlow" and fix synth_intel
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-01-09 18:42:19 +01:00
Clifford Wolf
a96c775a73
Add support for "yosys -E"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-01-07 16:36:13 +01:00
Clifford Wolf
446ccf1f05
Bugfix in hierarchy blackbox module port width handling
2018-01-07 16:35:22 +01:00
Clifford Wolf
c80315cea4
Bugfix in hierarchy handling of blackbox module ports
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-01-05 13:28:45 +01:00
Clifford Wolf
fefb652d56
Merge pull request #480 from Fatsie/liberty_value_expression
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Value of properties can be expression.
2018-01-04 13:30:00 +01:00
Clifford Wolf
2d140a44eb
Temporarily derive blackbox modules in hierarchy to evaluate port widths
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-01-04 13:23:29 +01:00
Staf Verhaegen
92eb841f0a
Value of properties can be expression.
...
Example found in the 2007.03 Liberty Reference Manual that was also found
in the wild:
input_voltage(CMOS) {
vil : 0.3 * VDD ;
vih : 0.7 * VDD ;
vimin : -0.5 ;
vimax : VDD + 0.5 ;
}
Current implementation just parses the expression but no interpretation is done.
2018-01-03 21:37:17 +00:00
Clifford Wolf
6132e6e72a
Fix a bug in clk2fflogic memory handling
2017-12-14 03:05:55 +01:00
Clifford Wolf
590e6961cb
Add clk2fflogic memory support
2017-12-14 02:07:31 +01:00
Clifford Wolf
88182e46d7
Check for memories in clk2fflogic
2017-12-13 19:14:34 +01:00
Clifford Wolf
ca2adc30c9
Add warnings for driver-driver conflicts between FFs (and other cells) and constants
2017-12-12 17:13:27 +01:00
Clifford Wolf
9ae25039fb
Add support for editline as replacement for readline
2017-11-08 02:55:00 +01:00
Clifford Wolf
4f31cb6dad
Add "ltp" command
2017-10-31 12:40:25 +01:00
Clifford Wolf
c238f45ecf
Fix memory corruption bug in opt_rmdff
2017-10-26 18:02:15 +02:00
Clifford Wolf
1e502ef5a0
Fix typo in opt_clean log message
2017-10-26 18:01:48 +02:00
Kaj Tuomi
e558b3284b
Fix input vector for reduce cells. Infinite loop fixed.
2017-10-17 09:58:01 +03:00
Clifford Wolf
716dbc9274
Revert 90be0d8
as it causes endless loops for some designs
2017-10-14 11:57:25 +02:00
Kaj Tuomi
90be0d800b
Fix input vector for reduce cells.
2017-10-12 13:05:10 +03:00
Clifford Wolf
7c57d8fbb4
Rewrite ABC output to include proper net names in timing report
2017-10-10 13:32:58 +02:00
Clifford Wolf
3f22f48eeb
Add blackbox command
2017-10-04 18:30:42 +02:00
Andrew Zonenberg
2b65b65d70
Added missing "break"
2017-09-15 17:54:52 -07:00
Andrew Zonenberg
7b3966714c
Implemented off-chain support for extract_reduce
2017-09-15 13:59:18 -07:00
Andrew Zonenberg
3404934c9c
extract_reduce now only removes the head of the chain, relying on "clean" to delete upstream cells. Added "-allow-off-chain" flag, but it's currently ignored.
2017-09-15 13:59:05 -07:00
Clifford Wolf
ce78717e36
Merge pull request #412 from azonenberg/reduce-fixes
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extract_reduce: Fix segfault on "undriven" inputs
2017-09-14 22:36:25 +02:00
Robert Ou
ab1bf8d661
extract_reduce: Fix segfault on "undriven" inputs
...
This is easily triggered when un-techmapping if the technology-specific
cell library isn't loaded. Outputs of technology-specific cells will be
seen as inputs, and nets using those outputs will be seen as undriven.
Just ignore these cells because they can't be part of a reduce chain
anyways.
2017-09-14 12:54:44 -07:00
Clifford Wolf
498526cc0b
Merge pull request #411 from azonenberg/counter-extraction-fixes
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Various improvements and bug fixes to extract_counter
2017-09-14 21:44:26 +02:00
Andrew Zonenberg
66e8986ae7
Minor changes to opt_demorgan requested during code review
2017-09-14 10:35:25 -07:00
Andrew Zonenberg
367d6b2194
Fixed bug where counter extraction on non-GreenPAK devices incorrectly handled parallel counter output
2017-09-14 10:27:10 -07:00
Andrew Zonenberg
c8f2f082c6
Added support for inferring counters with reset to full scale instead of zero
2017-09-14 10:26:43 -07:00
Andrew Zonenberg
122532b7e1
Added RESET_TO_MAX parameter to $__COUNT_ cell. Cannot yet be extracted.
2017-09-14 10:26:32 -07:00
Andrew Zonenberg
0484ad666d
Added support for inferring counters with active-low reset
2017-09-14 10:26:21 -07:00
Andrew Zonenberg
a84172b23b
Initial support for extraction of counters with clock enable
2017-09-14 10:26:10 -07:00
Andrew Zonenberg
c4a70a8cc3
Fixed typo in comment. Fixed bug where extract_counter would create up counters when it meant to create down counters.
2017-09-14 10:25:51 -07:00
Andrew Zonenberg
6da5d36968
Initial version of opt_demorgan is functioning for AND/OR gates. Not the prettiest results for bus inputs, but this can be improved
2017-09-12 18:47:46 -07:00
Clifford Wolf
f9d023c53f
Add src attribute to extra cells generated by proc_dlatch
2017-09-09 10:18:08 +02:00
Clifford Wolf
7d41c5e177
Further improve extract_fa (but still buggy)
2017-09-02 16:39:17 +02:00
Clifford Wolf
18609f3df8
Merge branch 'master' of github.com:cliffordwolf/yosys
2017-09-01 12:35:09 +02:00
Clifford Wolf
8a66bd30c6
Update more stuff to use get_src_attribute() and set_src_attribute()
2017-09-01 12:26:55 +02:00
Jason Lowdermilk
8dc6083de7
updated to use get_src_attribute() and set_src_attribute().
2017-08-31 14:51:56 -06:00
Andrew Zonenberg
ed1e3ed39b
extract_counter: Added optimizations to remove unused high-order bits
2017-08-30 18:15:12 -07:00
Andrew Zonenberg
634f18be96
extract_counter: Minor changes requested to comply with upstream policy, fixed a few typos
2017-08-30 16:28:25 -07:00
Jason Lowdermilk
32c0f1193e
Add support for source line tracking through synthesis phase
2017-08-29 14:46:35 -06:00
Andrew Zonenberg
3fc1b9f3fd
Finished refactoring counter extraction to be nice and generic. Implemented techmapping from $__COUNT_ to GP_COUNTx cells.
2017-08-28 22:18:57 -07:00
Andrew Zonenberg
46b01f05bb
Refactored extract_counter to be generic vs GreenPAK specific
2017-08-28 22:18:47 -07:00
Andrew Zonenberg
b5c15636c5
Refactoring: Renamed greenpak4_counters pass to extract_counter, moved it to techmap/ since it's going to become a generic pass
2017-08-28 22:18:34 -07:00
Clifford Wolf
908f34aafc
Rename recover_reduce to extract_reduce, fix args handling
2017-08-28 19:52:06 +02:00
Clifford Wolf
3aad3ed3da
Merge branch 'recover-reduce' of https://github.com/azonenberg/yosys into azonenberg-recover-reduce
2017-08-28 19:46:17 +02:00
Clifford Wolf
ebbb0e9479
Further improve extract_fa pass
2017-08-28 19:43:26 +02:00
Robert Ou
849b885775
recover_reduce: Update documentation
...
The documentation now describes the commands performed in the deleted
recover_reduce script.
2017-08-27 02:19:19 -07:00
Robert Ou
74d0f17fd4
recover_reduce: Reindent using tabs
2017-08-27 02:12:41 -07:00
Robert Ou
8a5887464c
recover_reduce: Rename recover_reduce_core to recover_reduce
...
Clifford has commented on PR #387 stating that he does not like the
driver script and would prefer to only have the core script with
appropriate notes in the documentation.
Also rename to .cc (rather than .cpp) for consistency.
2017-08-27 02:01:32 -07:00
Robert Ou
99dad40ed0
recover_reduce: Add driver script for the $reduce_* recover feature
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Conflicts:
passes/techmap/Makefile.inc
2017-08-27 01:57:20 -07:00
Robert Ou
8b7dc792ee
recover_reduce_core: Finish implementing the core function
2017-08-27 01:56:49 -07:00
Robert Ou
fa310c98f8
recover_reduce_core: Initial commit
...
Conflicts:
passes/techmap/Makefile.inc
2017-08-27 01:56:49 -07:00
Clifford Wolf
68c42f3a19
Don't track , ... contradictions through x/z-bits
2017-08-25 16:18:17 +02:00
Clifford Wolf
db6d78a186
Add removing of redundant pairs of bits in ==, ===, !=, and !== to opt_expr
2017-08-25 16:02:15 +02:00
Clifford Wolf
382cc90c65
Further improve extract_fa (seems to be fully functional now)
2017-08-25 13:41:54 +02:00
Clifford Wolf
0bf612506c
Rename "adders" to "extract_fa"
2017-08-25 12:04:40 +02:00
Clifford Wolf
15cdda7c4b
Towards more generic "adder" function extractor
2017-08-23 14:20:10 +02:00
Clifford Wolf
51cbec7f75
Add experimental adders pass
2017-08-22 13:52:13 +02:00
Clifford Wolf
df3e6e1ec9
Remove some dead code from fsm_map
2017-08-21 15:02:16 +02:00
Clifford Wolf
ca53fba44a
Rename "singleton" pass to "uniquify"
2017-08-20 12:31:50 +02:00
Clifford Wolf
d38a64b1cf
More intuitive handling of "cd .." for singleton modules
2017-08-19 00:15:12 +02:00
Clifford Wolf
bbdf7d9c66
Add "sim -zinit -rstlen"
2017-08-18 12:54:17 +02:00
Clifford Wolf
d30cc60ba9
Add "sim" support for memories
2017-08-18 11:44:50 +02:00
Clifford Wolf
0be738eaac
Add support for assert/assume/cover to "sim" command
2017-08-18 10:24:14 +02:00
Clifford Wolf
92e4b5aa77
Add writeback mode to "sim" command
2017-08-17 15:54:51 +02:00
Clifford Wolf
7b4f3f86c3
Improve "sim" command
2017-08-17 12:27:08 +02:00
Clifford Wolf
75046aa531
Add "sim" command skeleton
2017-08-16 13:05:21 +02:00
Clifford Wolf
88983f5012
Mostly coding style related fixes in rmports pass
2017-08-15 11:32:35 +02:00
Clifford Wolf
9fe6bc48a9
Merge branch 'rmports' of https://github.com/azonenberg/yosys into azonenberg-rmports
2017-08-15 11:19:55 +02:00
Robert Ou
9a64ba3338
abc: Allow +/ filenames in the abc command
2017-08-14 12:11:11 -07:00
Andrew Zonenberg
15e41d6363
rmports: Now remove ports from cell instances if we optimized them out of that cell
2017-08-14 11:44:05 -07:00
Andrew Zonenberg
0ee27d0226
ProcessModule is no longer virtual (why was it in the first place?)
2017-08-14 11:18:09 -07:00
Andrew Zonenberg
bd2ac68769
rmports now works on all modules in the design, not just the top.
2017-08-14 11:16:44 -07:00
Andrew Zonenberg
d5e5bbad86
Updated Makefile to reflect opt_rmports being renamed to rmports
2017-08-14 11:04:56 -07:00
Andrew Zonenberg
1a6a23f91a
Renamed opt_rmports pass to rmports
2017-08-14 11:00:45 -07:00
Andrew Zonenberg
1bb150c231
Improved handling of constant connections in opt_rmports
2017-08-14 10:28:19 -07:00
Andrew Zonenberg
2877d5e504
Fixed handling of cell ports that aren't wires
2017-08-14 10:28:16 -07:00
Andrew Zonenberg
3dd7f42e2b
opt_rmports: Fixed incorrect handling of multi-bit nets
2017-08-14 10:28:11 -07:00
Andrew Zonenberg
66aac06eee
Removed commented out debug code
2017-08-14 10:28:04 -07:00
Andrew Zonenberg
cca3cb5fbb
Added opt_rmports pass (remove unconnected ports from top-level modules)
2017-08-14 10:27:59 -07:00
Clifford Wolf
007f29b9c2
Add support for set-reset cell variants to opt_rmdff
2017-08-09 13:29:52 +02:00
Clifford Wolf
c4a7958f70
Add handling of constant reset signals to opt_rmdff
2017-08-06 13:27:18 +02:00
Clifford Wolf
5c09f24e48
Fix typo in "abc" pass help message
2017-07-29 16:21:58 +02:00
Clifford Wolf
e7d1277a2c
Add consolidation of init attributes to opt_clean, some opt_clean log fixes
2017-07-29 00:10:33 +02:00
Clifford Wolf
649bb9374f
Add "opt_expr -fine" feature to remove neutral bits from reduce and logic operators
2017-07-26 18:28:55 +02:00
Clifford Wolf
b6bd12fade
Add error for cell output ports that are connected to constants
2017-07-22 15:08:30 +02:00
Clifford Wolf
b3bc7068d1
Fix handling of empty cell port assignments (i.e. ignore them)
2017-07-21 19:32:31 +02:00
Clifford Wolf
c00d8a5b73
Add $alu to list of supported cells for "stat -width"
2017-07-14 11:32:49 +02:00
Salvador E. Tropea
ca23554528
Excluded $_TBUF_ from opt_merge pass
2017-07-03 13:21:20 -03:00
Clifford Wolf
0a02cdb93b
Fix and_or_buffer optimization in opt_expr for signed operators
2017-07-01 16:05:26 +02:00
Clifford Wolf
0f217080cf
Add "design -import"
2017-06-30 19:18:52 +02:00
Clifford Wolf
8952bd6f45
Add chtype command
2017-06-30 17:57:34 +02:00
Clifford Wolf
18c030a8c9
Add $tribuf to opt_merge blacklist
2017-06-30 17:44:44 +02:00
Clifford Wolf
155a80dfb7
Fix handling of init values in "abc -dff" and "abc -clk"
2017-06-20 15:32:23 +02:00
Clifford Wolf
f6421c83a2
Switched abc "clock domain not found" error to log_cmd_error()
2017-06-20 04:22:34 +02:00
Clifford Wolf
05df3dbee4
Add "setundef -anyseq"
2017-05-28 11:59:05 +02:00
Clifford Wolf
9ed4c9d710
Improve write_aiger handling of unconnected nets and constants
2017-05-28 11:31:35 +02:00
Clifford Wolf
fad52abf70
Add aliases for common sets of gate types to "abc -g"
2017-05-24 11:39:05 +02:00
Clifford Wolf
05cdd58c8d
Add $_ANDNOT_ and $_ORNOT_ gates
2017-05-17 09:08:29 +02:00
Clifford Wolf
3bbac5c141
Fix equiv_simple, old behavior now available with "equiv_simple -short"
2017-04-28 18:57:53 +02:00
Larry Doolittle
2021ddecb3
Squelch trailing whitespace
2017-04-12 15:11:09 +02:00
Clifford Wolf
dee4ec1661
Fix gcc compiler warning
2017-04-05 11:21:06 +02:00
Clifford Wolf
180d704568
Disable opt_merge for $anyseq and $anyconst
2017-02-28 22:17:00 +01:00
Clifford Wolf
1a6c02a532
Add "chformal -assert2assume" and friends
2017-02-28 00:00:44 +01:00
Clifford Wolf
db7fc0e32d
Add "chformal" pass
2017-02-27 13:25:28 +01:00
Clifford Wolf
5f1d0b1024
Add $live and $fair cell types, add support for s_eventually keyword
2017-02-25 10:36:39 +01:00
Clifford Wolf
cf25dc9ce7
Copy attributes to _TECHMAP_REPLACE_ cells
2017-02-16 12:28:42 +01:00
Clifford Wolf
69468d5a16
Do not fix port widths on any blackbox instances
2017-02-13 17:07:38 +01:00
Clifford Wolf
db7314bc02
Fix techmap for inout ports connected to inout ports
2017-02-13 16:55:25 +01:00
Clifford Wolf
76c4ee096b
Do not eagerly fix port widths on parameterized cells
2017-02-12 17:42:57 +01:00
Clifford Wolf
95dae6d416
Fixed some "used uninitialized" warnings in opt_expr
2017-02-11 10:50:48 +01:00
Clifford Wolf
a5bfeb9e07
Add optimization of (a && 1'b1) and (a || 1'b0)
2017-02-11 10:05:00 +01:00
C-Elegans
94b272077d
Fix issue #306 , "Bug in opt -full"
...
Add check for whether the high bit in the constant expression is greater
than the width of the variable, and optimizes that to a constant 1 or
0
2017-02-10 10:38:02 -05:00
Clifford Wolf
e6cc67b46f
Fix handling of init attributes with strange width
2017-02-09 16:06:58 +01:00
Clifford Wolf
3928482a3c
Add $cover cell type and SVA cover() support
2017-02-04 14:14:26 +01:00
Clifford Wolf
8927e19b13
Update ABC scripts to use "&nf" instead of "map"
2017-02-01 11:15:20 +01:00
Clifford Wolf
ffbe8d41f3
Fix indenting and log messages in code merged from opt_compare_pr
2017-01-31 16:20:56 +01:00
Clifford Wolf
19a980277f
Merge branch 'opt_compare_pr' of https://github.com/C-Elegans/yosys into C-Elegans-opt_compare_pr
2017-01-31 15:54:41 +01:00
Clifford Wolf
7481ba4750
Improve opt_rmdff support for $dlatch cells
2017-01-31 10:15:04 +01:00
C-Elegans
a94c3694d7
Refactor and generalize the comparision optimization
...
Generalizes the optimization to:
a < C,
a >= C,
C > a,
C <= a
2017-01-30 17:52:16 -05:00
Clifford Wolf
fe29869ec5
Add $ff and $_FF_ support to equiv_simple
2017-01-30 10:50:38 +01:00
Clifford Wolf
45e10c1c89
Be more conservative with merging large cells into FSMs
2017-01-26 09:19:28 +01:00
Clifford Wolf
49b8160488
Add warnings for quickly growing FSM table size in fsm_expand
2017-01-26 09:05:59 +01:00
C-Elegans
2fa0fd4a37
Do not use b.as_int() in calculation of bit set
2017-01-21 12:58:26 -05:00
C-Elegans
84f9cd0025
Optimize compares to powers of 2
...
Remove opt_compare and put comparison pass in opt_expr
assuming a [7:0] is unsigned
a >= (1<<x) becomes |a[7:x]
a < (1<<x) becomes !a[7:x]
Additionally:
a >= 0 becomes constant true,
a < 0 becomes constant false
delete opt_compare.cc
revert opt.cc to commit b7cfb7dbd
(remove opt_compare step)
2017-01-16 13:45:50 -05:00
Austin Seipp
6781543244
passes/hierarchy: delete some dead code
...
Signed-off-by: Austin Seipp <aseipp@pobox.com>
2017-01-15 16:39:12 -06:00
C-Elegans
943389cdd5
Fix issue #269 , optimize signed compare with 0
...
add opt_compare pass and add it to opt
for a < 0:
if a is signed, replace with a[max_bit-1]
for a >= 0:
if a is signed, replace with ~a[max_bit-1]
2017-01-15 13:38:29 -05:00
Clifford Wolf
0cac95ea94
Added "check -initdrv"
2017-01-04 18:12:41 +01:00
Clifford Wolf
f0df7dd796
Added cell port resizing to hierarchy pass
2017-01-01 23:03:44 +01:00
Clifford Wolf
b1cdf772eb
Added "design -reset-vlog"
2016-11-30 11:25:55 +01:00
Clifford Wolf
ac7a175a3c
Improved equiv_purge log output
2016-11-29 13:30:35 +01:00
Clifford Wolf
e444e59963
Added wire start_offset and upto handling to splitnets cmd
2016-11-23 13:54:33 +01:00
Clifford Wolf
55785a96eb
Improved ABC default scripts
2016-11-19 18:20:54 +01:00
Clifford Wolf
70d7a02cae
Added support for hierarchical defparams
2016-11-15 13:35:19 +01:00
Clifford Wolf
1827a48964
Minor bugfix in submod
2016-11-09 13:13:26 +01:00
Clifford Wolf
97ac77513f
Bugfix in "setundef" pass
2016-11-08 18:53:36 +01:00
Clifford Wolf
ef603c6fe1
Implemented "scc -set_attr"
2016-11-06 00:04:10 +01:00
Clifford Wolf
914aa8a5d3
Bugfix in "scc" command
2016-11-06 00:03:35 +01:00
Clifford Wolf
308a4b4a1b
Bugfix in "hierarchy -check"
2016-11-02 20:09:57 +01:00
Clifford Wolf
b63cace90f
Added support for fsm_encoding="user"
2016-11-02 13:15:49 +01:00
Clifford Wolf
0c8e973d32
Added "fsm_expand -full"
2016-11-02 09:31:39 +01:00
Clifford Wolf
d9d38eeedb
Bugfix in fsm_map for FSMs without reset state
2016-10-25 23:21:37 +02:00
Clifford Wolf
aa72262330
Added avail params to ilang format, check module params in 'hierarchy -check'
2016-10-22 11:05:49 +02:00
Clifford Wolf
3655d7fea7
Added "setparam -type"
2016-10-19 13:54:04 +02:00
Clifford Wolf
15fb56697a
Bugfix in "miter -assert" handling of assumptions
2016-10-17 14:56:58 +02:00
Clifford Wolf
6425d34e73
Added clk2fflogic support for $dffsr and $dlatch
2016-10-17 13:28:55 +02:00
Clifford Wolf
3a09d6bb65
Improvements and bugfixes in clk2fflogic
2016-10-16 23:03:29 +02:00
Clifford Wolf
74702b04c2
Build fixes for VS 2015
2016-10-16 20:37:02 +02:00
Clifford Wolf
fa535c0b00
Some minor build fixes for Visual C
2016-10-14 18:36:02 +02:00
Clifford Wolf
e4c5ee9b89
Avoid using strcasecmp()
2016-10-14 18:20:36 +02:00
Clifford Wolf
2733994aeb
Added clk2fflogic
2016-10-14 14:55:07 +02:00
Clifford Wolf
2ef454c3f5
Added opt_rmdff support for $ff cells
2016-10-14 13:02:36 +02:00
Clifford Wolf
53655d173b
Added $global_clock verilog syntax support for creating $ff cells
2016-10-14 12:33:56 +02:00
Clifford Wolf
ffbb4e992e
Added MEMID handling to "flatten" pass
2016-10-14 10:36:37 +02:00
Clifford Wolf
ee91350add
Added "zinit" pass
2016-10-12 12:05:19 +02:00
Clifford Wolf
8ebba8a35f
Added $ff and $_FF_ cell types
2016-10-12 01:18:39 +02:00
Clifford Wolf
ed519f578e
Added "opt_rmdff -keepdc"
2016-09-30 17:02:38 +02:00
Clifford Wolf
e788ad4885
Cosmetic fix in test_autotb.cc
2016-09-19 20:43:43 +02:00
Clifford Wolf
5e155aa121
Avoid creating very long strings in test_autotb
2016-09-19 10:20:20 +02:00
Clifford Wolf
d8ad889594
Bugfix in techmap parameter handling
2016-09-14 20:46:54 +02:00
Kaj Tuomi
df4ab169a7
Typo fix.
2016-09-08 10:57:16 +03:00
Clifford Wolf
cb7dbf4070
Improvements in assertpmux
2016-09-07 12:42:16 +02:00
Clifford Wolf
ab18e9df7c
Added assertpmux
2016-09-07 00:28:01 +02:00
Clifford Wolf
f3f5a02045
Added "tee +INT -INT"
2016-09-06 17:43:24 +02:00
Clifford Wolf
fc5281b3f7
Run log_flush() before solving in sat command
2016-09-06 17:35:25 +02:00
Clifford Wolf
4ea7054b56
Improved init spec handling in opt_rmdff, modernized the code a bit
2016-08-30 01:34:04 +02:00
Clifford Wolf
eae390ae17
Removed $predict again
2016-08-28 21:35:33 +02:00
Clifford Wolf
66582964bc
Improved "show" help message
2016-08-28 12:34:36 +02:00
Clifford Wolf
23afeadb5e
Fixed handling of transparent bram rd ports on ROMs
2016-08-27 17:06:22 +02:00
Clifford Wolf
cad40fc874
Fixed bug in memory_share for memory ports with different ABITS
2016-08-22 14:26:33 +02:00
Clifford Wolf
d77a914683
Added "wreduce -memx"
2016-08-20 12:52:50 +02:00
Clifford Wolf
15ef608453
Added memory_memx pass, "memory -memx", and "prep -memx"
2016-08-19 19:48:26 +02:00
Clifford Wolf
f6629b9c29
Optimize memory address port width in wreduce and memory_collect, not verilog front-end
2016-08-19 18:38:25 +02:00
Clifford Wolf
b3a01451a5
Bugfix in test_autotb
2016-08-18 13:43:12 +02:00
Clifford Wolf
00f29d5e5c
Fixed use-after-free dict<> usage pattern in hierarchy.cc
2016-08-16 09:07:13 +02:00
Clifford Wolf
321e15b0bf
Minor fixes in show command
2016-08-16 00:36:24 +02:00
Clifford Wolf
73b7232ec8
Fixed some compiler warnings in attrmap command
2016-08-10 13:44:08 +02:00
Clifford Wolf
b0aab4e304
Added "attrmap" command
2016-08-09 19:56:55 +02:00
Clifford Wolf
3c6d31fd06
Added "attrmvcp" pass
2016-08-09 11:18:48 +02:00
Clifford Wolf
9d15529214
Undo "preserve wire attributes in iopadmap" change (it was OK before)
2016-08-08 11:47:35 +02:00
Clifford Wolf
88a67afa7d
Added "test_autotb -seed" (and "autotest.sh -S")
2016-08-06 13:32:29 +02:00
Clifford Wolf
90c17aad56
preserve wire attributes in iopadmap
2016-08-06 13:24:59 +02:00
Clifford Wolf
5d6765a9d2
Added "insbuf" command
2016-08-02 10:37:19 +02:00
Clifford Wolf
8537c4d206
Renamed AbstractCellEdgesDatabase::add_cell() to add_edges_from_cell()
2016-07-25 16:39:25 +02:00
Clifford Wolf
b1c432af56
Improvements in CellEdgesDatabase
2016-07-24 17:21:53 +02:00
Clifford Wolf
f162b858f2
Added CellEdgesDatabase API
2016-07-24 13:59:57 +02:00
Clifford Wolf
54966679df
Moved SatHelper::setup_init() code to SatHelper::setup()
2016-07-24 12:18:39 +02:00
Clifford Wolf
34e833103b
Added $initstate support to "sat" command
2016-07-23 17:01:03 +02:00
Clifford Wolf
d7763634b6
After reading the SV spec, using non-standard predict() instead of expect()
2016-07-21 13:34:33 +02:00
Clifford Wolf
721f1f5ecf
Added basic support for $expect cells
2016-07-13 16:56:17 +02:00
Clifford Wolf
e92998a79c
Minor bugfix in FSM reset state detection
2016-07-12 09:46:15 +02:00
Clifford Wolf
b5a9fba0db
Further improved fsm_detect output, attempt to detect self-resetting circuits
2016-07-09 14:02:49 +02:00
Clifford Wolf
d63ffabacb
Added printing of some warning messages to fsm_detect
2016-07-09 13:23:06 +02:00
Clifford Wolf
6ed6b3cb6d
Replaced "select -assert-limit" with -assert-max and -assert-min
2016-07-01 12:24:13 +02:00
eshellko
9a742f4069
Added 'assert-limit' option for 'select' command
...
For resource limited designs such as FPGA it can be useful to specify limit of specific resources available on board. So user can check if he should change RTL as early as mapping done.
2016-07-01 10:24:22 +04:00
Clifford Wolf
541083cf32
Bugfix in "abc -script" handling
2016-06-19 22:19:19 +02:00
Clifford Wolf
ca91bccb6b
Added "deminout"
2016-06-19 13:08:16 +02:00
Clifford Wolf
3380281e15
Added "dc2" to default ABC scripts
2016-06-17 20:15:35 +02:00
Clifford Wolf
f498204ae4
Added "abc -I <num> -P <num>"
2016-06-17 19:39:35 +02:00
Clifford Wolf
95757efb25
Improved support for $sop cells
2016-06-17 16:31:16 +02:00
Clifford Wolf
52bb1b968d
Added $sop cell type and "abc -sop"
2016-06-17 13:50:09 +02:00
Clifford Wolf
c3365034e9
Updated ABC to hg rev b5df6e2b76f0
2016-06-17 11:16:31 +02:00
Clifford Wolf
99edf24966
Added "nlutmap -assert"
2016-06-09 11:47:41 +02:00
Clifford Wolf
2032e6d8e4
Added "proc_mux -ifx"
2016-06-06 17:15:50 +02:00
Clifford Wolf
dcf576641b
Added "setundef -init"
2016-06-03 11:38:31 +02:00
Clifford Wolf
d2695e2bfa
Fix all undef-muxes in dlatch input cone
2016-06-02 14:37:07 +02:00
Clifford Wolf
adfc80727c
Avoid creating undef-muxes when inferring latches in proc_dlatch
2016-06-01 13:25:06 +02:00
Clifford Wolf
11f7b8a2a1
Added opt_expr support for div/mod by power-of-two
2016-05-29 12:17:36 +02:00
Clifford Wolf
611f121cb9
Fixed "scc" for cells that have feedback singals _and_ are part of a larger loop
2016-05-27 16:33:13 +02:00
Marcus Comstedt
e22e4d59b8
Made the expansion order of hierarchy deterministic
2016-05-22 16:41:26 +02:00
Clifford Wolf
1e227caf72
Improvements and fixes in autotest.sh script and test_autotb
2016-05-20 16:58:02 +02:00
Kaj Tuomi
8c3bc2ac0d
Close opened dump file.
2016-05-19 11:53:29 +03:00
Kaj Tuomi
f6221ade95
Fix for Modelsim transcript line warp issue #164
2016-05-19 11:34:38 +03:00
Clifford Wolf
ffcdc53a18
Don't sign-extend memory bram initialization data
2016-05-15 00:05:30 +02:00
Clifford Wolf
c3f6e0ea85
Added support for "keep" attribute to shregmap
2016-05-07 09:33:16 +02:00
Clifford Wolf
aadca148da
Fixed preservation of important attributes in techmap
2016-05-06 13:59:30 +02:00
Andrew Zonenberg
3486637b19
Changed port names in greenpak shregmap
2016-05-04 17:04:50 -07:00
Clifford Wolf
9647dc3c07
Added tristate buffer support to iopadmap
2016-05-04 22:48:02 +02:00
Clifford Wolf
658f93663b
Fixed iopadmap attribute handling
2016-05-04 10:48:23 +02:00
Clifford Wolf
e01464e2ac
Added "qwp -v"
2016-04-28 23:17:30 +02:00
Clifford Wolf
0d2923cccd
Connections between inputs and inouts are driven by the input
2016-04-26 19:49:05 +02:00
Clifford Wolf
958fb29c76
Fixed test_autotb for modules with many cell ports
2016-04-25 16:37:11 +02:00
Clifford Wolf
93e107e455
Fixed proc_mux performance bug
2016-04-25 10:43:04 +02:00
Clifford Wolf
b1d6f05fa2
Fixed performance bug in proc_dlatch
2016-04-24 19:29:56 +02:00
Clifford Wolf
096c25d29d
Improvements in greenpak4 shreg mapping
2016-04-23 23:10:13 +02:00
Andrew Zonenberg
7f16784f3c
Merge https://github.com/cliffordwolf/yosys
2016-04-23 12:22:08 -07:00
Clifford Wolf
e13c66122e
Added "shregmap -zinit" for greenpak4 tech
2016-04-23 20:20:21 +02:00
Andrew Zonenberg
2849fd486e
Fixed typo in help text
2016-04-22 23:01:39 -07:00
Clifford Wolf
7311be4028
Added "shregmap -tech greenpak4"
2016-04-22 19:42:08 +02:00
Clifford Wolf
965b0d59b5
More flexible handling of initialization values
2016-04-22 12:13:06 +02:00
Clifford Wolf
0bc95f1e04
Added "yosys -D" feature
2016-04-21 23:28:37 +02:00
Clifford Wolf
1565d1af69
Fixed performance bug in "share" pass
2016-04-21 19:47:25 +02:00
Clifford Wolf
f38ca3e18f
Improvements in opt_expr
2016-04-21 14:23:04 +02:00
Clifford Wolf
1761d08dd2
Bugfix and improvements in memory_share
2016-04-21 14:22:58 +02:00
Clifford Wolf
f1fa757d0e
Added "shregmap -params"
2016-04-18 11:58:21 +02:00
Clifford Wolf
525651c8f6
Added "shregmap -zinit" and "shregmap -init"
2016-04-18 11:44:10 +02:00
Clifford Wolf
ce7c980ec7
Improvements in "shregmap"
2016-04-17 15:37:22 +02:00
Clifford Wolf
de647a390c
Added "shregmap" pass
2016-04-16 23:20:49 +02:00
Clifford Wolf
fbdb8e7b3e
Fixed copy&paste error in log message in lut2mux
2016-04-16 23:20:34 +02:00
Clifford Wolf
6041f780c3
Prefer noninverting FFs in dfflibmap
2016-04-05 12:51:04 +02:00
Clifford Wolf
eaac5bfbc7
Improved formatting of "sat" output tables
2016-04-05 08:26:10 +02:00
Clifford Wolf
6cafd08ac1
Improved opt_merge support for $pmux cells
2016-03-31 09:58:55 +02:00
Clifford Wolf
e5dd5c0bcc
Preserve empty $pmux default cases
2016-03-31 09:57:23 +02:00
Clifford Wolf
e2f6d61c00
Typo fixes in opt_expr and opt_merge
2016-03-31 09:56:56 +02:00
Clifford Wolf
ec93680bd5
Renamed opt_share to opt_merge
2016-03-31 08:52:49 +02:00
Clifford Wolf
1d0f0d668a
Renamed opt_const to opt_expr
2016-03-31 08:46:56 +02:00
Andrew Zonenberg
984561c034
Renamed counters pass to greenpak4_counters
2016-03-30 22:52:01 -07:00
Andrew Zonenberg
1ae33344f4
Added initial implementation of "counters" pass to synth_greenpak4. Can only infer non-resettable down counters for now.
2016-03-30 22:40:14 -07:00
Andrew Zonenberg
1b42e0c471
Reduced log verbosity
2016-03-30 22:03:50 -07:00
Andrew Zonenberg
ad19e0c64a
Continued work on counter extraction. Can recognize compatible RTL counters but not replace with hard macros.
2016-03-30 21:54:23 -07:00
Andrew Zonenberg
d16d05e415
Merge https://github.com/cliffordwolf/yosys
2016-03-30 20:38:18 -07:00
Andrew Zonenberg
dd7204c0bd
Fixed typo in log message
2016-03-30 20:30:03 -07:00
Andrew Zonenberg
489caf32c5
Initial work on greenpak4 counter extraction. Doesn't work but a decent start
2016-03-30 01:07:20 -07:00
Clifford Wolf
a47f69536a
Added support for installed plugins
2016-03-30 10:02:03 +02:00
Clifford Wolf
9717495401
Fixed handling of inverters (aka 1-input luts) in nlutmap
2016-03-23 08:56:08 +01:00
Clifford Wolf
043fa0fad0
Cleanup abstract modules at end of "hierarchy -top"
2016-03-21 16:37:35 +01:00
Clifford Wolf
2c7e107d7a
Support for abstract modules in chparam
2016-03-21 16:37:35 +01:00
Clifford Wolf
bb9374b67c
Improvements in ABCEXTERNAL handling
2016-03-19 20:02:40 +01:00
Sergey Kvachonok
2656b2c55a
Support calling out to an external ABC.
...
$ make ABCEXTERNAL=my-abc && make ABCEXTERNAL=my-abc install
configures yosys to use an external ABC executable instead of
building and installing the in-tree ABC copy (yosys-abc).
2016-03-19 18:36:18 +03:00
Clifford Wolf
c4aaed099f
Using "mfs" and "lutpack" in ABC lut mapping
2016-03-07 11:14:11 +01:00
Clifford Wolf
bcc873b805
Fixed some visual studio warnings
2016-02-13 17:31:24 +01:00
Clifford Wolf
0d7fd2585e
Added "int ceil_log2(int)" function
2016-02-13 16:52:16 +01:00
Clifford Wolf
825b99efc1
Added "stat -liberty" for calculating chip area
2016-02-04 12:26:13 +01:00
Clifford Wolf
801c022457
Improved dffsr2dff pass
2016-02-02 19:42:49 +01:00
Clifford Wolf
d69395ca08
Added dffsr2dff
2016-02-02 17:19:01 +01:00
Clifford Wolf
d6592d5b99
Use alphanumerical order instead of idstring idx in opt_clean compare_signals()
2016-02-02 09:16:18 +01:00
Clifford Wolf
17372d8abd
Added "abc -luts" option, Improved Xilinx logic mapping
2016-02-01 12:40:32 +01:00
Clifford Wolf
9251553592
Improvements in dfflibmap (FFs with Q/QN outputs, DFFs from ADFFs)
2016-02-01 11:49:11 +01:00
Clifford Wolf
71f418c468
More clang sanitizer stuff
2016-01-31 19:55:48 +01:00
Clifford Wolf
8b3f8cd220
Added "equiv_struct -fwonly"
2016-01-08 10:59:16 +01:00
Clifford Wolf
f5008f4f8a
Bugfixes in equiv_struct
2016-01-08 09:57:28 +01:00
Clifford Wolf
d00c63c927
Added "submod -copy"
2016-01-08 09:08:12 +01:00
Clifford Wolf
c3fd03d722
Added "equiv_struct -maxiter <N>"
2016-01-06 13:54:54 +01:00
Clifford Wolf
1f8c47fb47
Added "equiv_add -try" mode
2016-01-06 13:54:00 +01:00
Clifford Wolf
1d62f8710f
Fixed "splitnets -ports" for hierarchical designs
2015-12-22 13:25:00 +01:00
Clifford Wolf
ab0c44d3ed
Added %R select expression
2015-12-20 13:35:58 +01:00
Clifford Wolf
1ea6db3db8
Improved proc_mux performance for huge always blocks
2015-12-02 22:02:20 +01:00
Clifford Wolf
e61c7f887a
Added torder command
2015-11-19 15:34:32 +01:00
Clifford Wolf
d98d99aec6
Added "abc -g"
2015-11-10 11:10:11 +01:00
Marcus Comstedt
8c2bdef36d
Fix a segfault in dffinit when the value has too few bits
...
The code was already trying to add the required number of bits, but
fell one short of the mark.
2015-11-08 19:16:56 +01:00
Clifford Wolf
1ec6429bad
Added "singleton" pass
2015-11-07 19:10:43 +01:00
Clifford Wolf
f401eeb0cf
Bugfix in mapping $tribuf to $_TBUF_
2015-11-05 12:37:43 +01:00
Clifford Wolf
ddf3e2dc65
Bugfix in memory_dff
2015-10-31 22:01:41 +01:00
Clifford Wolf
ccdbf41be6
Improvements in wreduce
2015-10-31 13:39:30 +01:00
Clifford Wolf
0c202a2549
Use mfp<> in equiv_mark
2015-10-27 19:15:35 +01:00
Clifford Wolf
27714acd8a
Improvements in equiv_struct
2015-10-25 22:04:20 +01:00
Clifford Wolf
d014ba2d0e
Major refactoring of equiv_struct
2015-10-25 19:31:29 +01:00
Clifford Wolf
207736b4ee
Import more std:: stuff into Yosys namespace
2015-10-25 19:30:49 +01:00
Clifford Wolf
da923c198e
Added "equiv_add -cell"
2015-10-25 14:35:40 +01:00
Clifford Wolf
83bd27bf6e
equiv_struct now creates equiv_merged attributes
2015-10-25 02:15:20 +02:00
Clifford Wolf
453736d918
Improvements in equiv_struct
2015-10-24 23:04:17 +02:00
Clifford Wolf
7f110e7018
renamed SigSpec::to_single_sigbit() to SigSpec::as_bit(), added is_bit()
2015-10-24 22:56:40 +02:00
Clifford Wolf
6af8076967
improvement in "stat"
2015-10-24 21:56:53 +02:00
Clifford Wolf
6fe48cf41e
equiv_purge bugfix, using SigChunk in Yosys namespace
2015-10-24 19:09:45 +02:00
Clifford Wolf
2a0f577f83
Fixed handling of driver-driver conflicts in wreduce
2015-10-24 13:44:35 +02:00
Clifford Wolf
4cec1c058d
Added equiv_mark command
2015-10-23 23:56:58 +02:00
Clifford Wolf
c35db8c19e
Disabled "Skipping blackbox module" msg in show command
2015-10-23 20:11:05 +02:00
Clifford Wolf
15a67392f1
Also merge $equiv cells in equiv_struct
2015-10-23 15:26:58 +02:00
Clifford Wolf
d19069b0fb
Improvements in equiv_struct
2015-10-23 15:11:57 +02:00
Clifford Wolf
84a07ffb8a
Added equiv_purge
2015-10-22 15:40:27 +02:00
Clifford Wolf
00e05b1310
Added equiv_struct command
2015-10-21 17:12:35 +02:00
Clifford Wolf
6416dfee93
Improved inout handling in equiv_make
2015-10-21 15:42:50 +02:00
Clifford Wolf
1d83854d84
Bugfixes in handling of "keep" attribute on wires
2015-10-15 14:57:28 +02:00
Clifford Wolf
eb1e3caae7
Fixed "flatten" for unconnected inout ports
2015-10-13 10:30:23 +02:00
Clifford Wolf
c58bd5dc30
Added edgetypes command
2015-09-27 11:53:20 +02:00
Clifford Wolf
281c1f4029
Some cleanups in qwp
2015-09-26 10:42:27 +02:00
Clifford Wolf
ddcfc99f8c
Added "test_cell -noeval"
2015-09-25 17:27:18 +02:00
Clifford Wolf
82028c42e0
Added wreduce $mul support and fixed signed $mul opt_const bug
2015-09-25 17:27:06 +02:00
Clifford Wolf
4864736167
Bugfix in bram read-enable code
2015-09-25 14:22:33 +02:00
Clifford Wolf
924d9d6e86
Added read-enable to memory model
2015-09-25 12:23:11 +02:00
Clifford Wolf
ec92c89659
Added pivoting to qwp solver
2015-09-24 22:16:37 +02:00
Clifford Wolf
69071bbc5f
Improved qwp performance
2015-09-24 21:50:37 +02:00
Clifford Wolf
b1e9cb332d
Added statistics summary to "qwp"
2015-09-24 21:22:24 +02:00
Clifford Wolf
3501f8e364
Fixed memory_bram for ROMs in BRAMs with write-enable inputs
2015-09-24 11:37:15 +02:00
Clifford Wolf
b66bf8bed1
Do not detect fsm state registers with init attribute
2015-09-21 11:54:00 +02:00
Clifford Wolf
11c27b5e69
Bugfix in "qwp" pass
2015-09-21 10:37:24 +02:00
Clifford Wolf
80898dcbc8
Improvements and fixes in "qwp" pass
2015-09-21 01:05:13 +02:00
Clifford Wolf
6329bea873
Added "qwp -dump"
2015-09-20 22:36:35 +02:00
Clifford Wolf
539c5eeb0f
Added "qwp" command
2015-09-20 18:28:46 +02:00
Clifford Wolf
598a475724
Added nlutmap
2015-09-18 21:57:34 +02:00
Clifford Wolf
c851f51656
Added lut2mux pass
2015-09-18 21:55:48 +02:00
Clifford Wolf
db548800b6
Added buffer detection to "abc -lut"
2015-09-18 20:12:56 +02:00
Clifford Wolf
452d4bf741
Added support for "dfflibmap -liberty +/..."
2015-09-18 11:55:57 +02:00
Clifford Wolf
51e1295d79
Added detection of "mux inverter" chains in opt_const
2015-09-18 11:55:31 +02:00
Clifford Wolf
b7535a6c75
Added $logic_not handling to fsm_detect
2015-09-18 10:46:50 +02:00
Clifford Wolf
e7c018e5d1
Fixed sharing of $memrd cells
2015-09-12 16:01:20 +02:00
Clifford Wolf
6f9a6fd783
Fixed port ordering in "splitnets" cmd
2015-09-01 13:10:36 +02:00
Clifford Wolf
b10ea0550d
gcc-4.6 build fixes
2015-09-01 12:51:23 +02:00
Clifford Wolf
24e7cf89bc
Fixed iopadmap help message
2015-08-31 16:49:42 +02:00
Clifford Wolf
92dce21f6e
Using dict<> and pool<> in alumacc pass
2015-08-31 16:26:01 +02:00
Clifford Wolf
f40d1b78b6
Added sat -show-regs, -show-public, -show-all
2015-08-18 17:14:30 +02:00
Clifford Wolf
246e362717
Bugfix in fsm_detect for complex muxtrees
2015-08-18 14:17:50 +02:00
Clifford Wolf
f43815054e
Properly clean up unused "init" attributes
2015-08-18 13:50:15 +02:00
Clifford Wolf
9c33172ece
Added tribuf command
2015-08-16 12:55:25 +02:00
Clifford Wolf
ff50bc2ac3
Added $tribuf and $_TBUF_ cell types
2015-08-16 12:54:52 +02:00
Clifford Wolf
ae09c89f62
Fixed opt_clean handling of inout ports
2015-08-16 09:50:17 +02:00
Larry Doolittle
6c00704a5e
Another block of spelling fixes
...
Smaller this time
2015-08-14 23:27:05 +02:00
Larry Doolittle
022f570563
Keep gcc from complaining about uninitialized variables
2015-08-14 23:26:49 +02:00
Clifford Wolf
0350074819
Re-created command-reference-manual.tex, copied some doc fixes to online help
2015-08-14 11:27:19 +02:00
Clifford Wolf
84bf862f7c
Spell check (by Larry Doolittle)
2015-08-14 10:56:05 +02:00
Clifford Wolf
80910d13a6
Merge branch 'master' of github.com:cliffordwolf/yosys
2015-08-13 09:52:06 +02:00
Clifford Wolf
08ad5409a2
Some ASCII encoding fixes (comments and docs) by Larry Doolittle
2015-08-13 09:30:20 +02:00
Clifford Wolf
e4ef000b70
Adjust makefiles to work with out-of-tree builds
...
This is based on work done by Larry Doolittle
2015-08-12 15:04:44 +02:00
Clifford Wolf
c43f38c81b
Improved handling of "keep" attributes in hierarchical designs in opt_clean
2015-08-12 14:10:14 +02:00
Clifford Wolf
667b015018
Merge pull request #70 from gaomy3832/bugfix
...
Remove unused blackbox modules in opt_clean.
2015-08-12 08:45:04 +02:00
Mingyu Gao
cbda56d178
Remove unused blackbox modules in opt_clean.
2015-08-11 09:51:08 -07:00
Mingyu Gao
8c4c62f3e1
Bugfix for cell hash cache option in opt_share.
2015-08-11 11:40:23 +02:00
Clifford Wolf
2185125760
Added missing ct_all setup to opt_clean
2015-08-11 07:54:32 +02:00
Mingyu Gao
021b4a2436
Bugfix for cell hash cache option in opt_share.
2015-08-10 13:01:44 -07:00
Clifford Wolf
883e09d8ed
Use MEMID as name for $mem cell
2015-08-09 13:35:44 +02:00
Clifford Wolf
8d6d5c30d9
Added WORDS parameter to $meminit
2015-07-31 10:40:09 +02:00
Clifford Wolf
3860c9a9f2
Fixed flatten $meminit handling
2015-07-30 21:43:41 +02:00
Clifford Wolf
4d0ba9b3b2
Fixed "check" command for inout ports
2015-07-27 09:54:58 +02:00
Clifford Wolf
2a613b1b66
Some cleanups in opt_rmdff
2015-07-25 12:09:57 +02:00
Clifford Wolf
badc5f7eb9
Added "miter -assert"
2015-07-25 12:09:57 +02:00
Clifford Wolf
2397078485
Keep modules with $assume (like $assert)
2015-07-25 12:09:57 +02:00
Clifford Wolf
914ae3401e
Improved $adff simplification
2015-07-24 14:12:50 +02:00
Clifford Wolf
ad919ae4e3
Fixed techmap processes error msg
2015-07-18 12:16:27 +02:00
Clifford Wolf
8393f70538
Some fixes in "select" command
2015-07-16 22:10:26 +02:00
Clifford Wolf
d2ff5d9994
Do not collect disabled $memwr cells
2015-07-06 13:28:00 +02:00
Clifford Wolf
766dd51447
Bugfix in fsm_extract
2015-07-03 18:42:36 +02:00
Clifford Wolf
6c84341f22
Fixed trailing whitespaces
2015-07-02 11:14:30 +02:00
Clifford Wolf
053058d781
Added opt_const -clkinv
2015-07-01 10:49:21 +02:00
Clifford Wolf
ee9188a5b4
Added logic-loop error handling to freduce
2015-06-30 17:11:46 +02:00
Clifford Wolf
77e89399a6
Bugfix in chparam
2015-06-30 01:38:34 +02:00
Clifford Wolf
caa274ada6
Added design->rename(module, new_name)
2015-06-30 01:37:59 +02:00
Clifford Wolf
99100f367d
Added "rename -top new_name"
2015-06-17 09:38:56 +02:00
Clifford Wolf
66910e15b2
Modernized memory_dff (and fixed a bug)
2015-06-14 16:15:51 +02:00
Clifford Wolf
f6eca509bb
Added "memory -nordff"
2015-06-14 15:47:11 +02:00
Clifford Wolf
4c733301e6
Fixed cstr_buf for std::string with small string optimization
2015-06-11 13:39:49 +02:00
Clifford Wolf
1ae360cf72
AigMaker refactoring
2015-06-10 23:00:12 +02:00
Clifford Wolf
56d4822719
Renamed "aig" to "aigmap"
2015-06-10 07:24:26 +02:00
Clifford Wolf
85287295b2
Fixed cellaigs port extending
2015-06-10 07:16:30 +02:00
Clifford Wolf
66f9ee412a
Added "aig" pass
2015-06-09 22:33:26 +02:00
Clifford Wolf
b57cb4a7fe
Merge clock inverters in memory_dff
2015-06-09 07:25:12 +02:00
Clifford Wolf
08f9b38a9c
Added opt_share -share_all
2015-05-31 14:24:34 +02:00
Clifford Wolf
522705cc28
Added liberty dont_use support to dfflibmap
2015-05-31 07:51:12 +02:00
Clifford Wolf
9f772eb970
Improved "flatten" handlings of inout ports
2015-05-23 10:14:53 +02:00
Clifford Wolf
4b6221478e
Added simple $dlatch support to opt_rmdff
2015-05-23 09:45:48 +02:00
Clifford Wolf
e122c2644e
preserve used $-wires with init attribute in opt_clean
2015-05-22 08:20:29 +02:00
Clifford Wolf
e5116eeb77
Generalized blifparse API
2015-05-17 15:10:37 +02:00
Clifford Wolf
7dad017c9c
abc/blifparse files reorganization
2015-05-17 14:44:28 +02:00
Clifford Wolf
c2f30e0de4
Added .barbuf support to abc BLIF parser
2015-05-13 06:45:12 +02:00
Clifford Wolf
7462618591
Fixed memory_unpack for initialized memories
2015-04-29 19:55:32 +02:00
Clifford Wolf
96be31de89
Preserve important attributes in splitnets
2015-04-29 07:44:57 +02:00
Clifford Wolf
f483dce7c2
Added $eq/$neq -> $logic_not/$reduce_bool optimization
2015-04-29 07:28:15 +02:00
Clifford Wolf
794d22969d
Added simplemap $lut support
2015-04-27 10:16:07 +02:00
Clifford Wolf
49859393bb
Improved attributes API and handling of "src" attributes
2015-04-24 22:04:05 +02:00
Clifford Wolf
11f77205f5
Fixed memory_share for unconditional write with part select to memory
2015-04-22 06:40:23 +02:00
Clifford Wolf
faa95dd845
don't consider blackbox modules in "sat" command
2015-04-18 09:29:03 +02:00
Clifford Wolf
9041f34233
Improved handling of init values in opt_rmdff
...
based on a patch by Mingyu Gao, user gaomy3832 on github
2015-04-18 08:04:31 +02:00
Clifford Wolf
8cdbcf6859
Bugfix for $_DFF_?_ in "dff2dffe -direct-match"
2015-04-17 21:35:59 +02:00
Clifford Wolf
e050467b89
Improved "maccmap" help message
2015-04-16 18:23:43 +02:00
Clifford Wolf
dc30b034f7
Fixed "dff2dffe -direct-match"
2015-04-16 11:47:59 +02:00
Clifford Wolf
f80d020f17
Added "dff2dffe -direct-match"
2015-04-16 11:30:17 +02:00
Clifford Wolf
2fc2f8f5b3
Added "splice -wires"
2015-04-13 19:28:12 +02:00
Clifford Wolf
e305d85807
Added handling of bool-output cells to "wreduce"
2015-04-13 19:27:49 +02:00
Clifford Wolf
7319951145
Added memory_bram "make_outreg" feature
2015-04-09 16:08:54 +02:00
Clifford Wolf
d176e613c2
Minor fixes in handling of "init" attribute
2015-04-09 15:12:26 +02:00
Clifford Wolf
be7b9b34ca
techmap code cleanup
2015-04-09 12:02:26 +02:00
Clifford Wolf
21a1cc1b60
Added support for "file names with blanks"
2015-04-08 12:14:34 +02:00
Clifford Wolf
aa0ab975b9
Removed "techmap -share_map" (use "-map +/filename" instead)
2015-04-08 12:13:53 +02:00
Clifford Wolf
8eadd8fb18
Added %M and %C select operators
2015-04-07 22:22:09 +02:00
Clifford Wolf
724cead61d
Added "pmuxtree" command
2015-04-07 20:27:10 +02:00
Clifford Wolf
1f33b2a490
Added "chparam -list"
2015-04-07 19:21:30 +02:00
Clifford Wolf
590f74d8f0
Added decoder generation to "muxcover"
2015-04-07 18:03:27 +02:00
Clifford Wolf
f7fb21f185
Added "muxcover" command
2015-04-07 15:42:25 +02:00
Clifford Wolf
c1af590f4e
typo fix
2015-04-07 07:43:01 +02:00
Clifford Wolf
329b841aac
Added "chparam" command
2015-04-07 07:30:14 +02:00
Clifford Wolf
169d1c4711
Added support for initialized brams
2015-04-06 17:06:15 +02:00
Clifford Wolf
a1c62b79d5
Avoid parameter values with size 0 ($mem cells)
2015-04-05 18:04:19 +02:00
Clifford Wolf
706631225e
Added $_MUX4_, $_MUX8_, and $_MUX16_ cell types
2015-04-05 09:45:14 +02:00
Clifford Wolf
c52a4cdeed
Added "dffinit", Support for initialized Xilinx DFF
2015-04-04 19:00:15 +02:00
Clifford Wolf
4b44907619
documentation improvements
2015-03-29 20:22:08 +02:00
Clifford Wolf
68bbb15214
Fixed detection of absolute paths in ABC for win32
2015-03-22 11:03:56 +01:00
Clifford Wolf
8b1e0bdd9e
Fixed handling of quotes in liberty parser
2015-03-18 16:03:19 +01:00
Clifford Wolf
aed4d763cf
Added hierarchy -auto-top
2015-03-18 08:33:40 +01:00
Clifford Wolf
ed15400fc6
Fixed bug in "hierarchy" for parametric designs
2015-03-04 15:52:34 +01:00
Clifford Wolf
1f1deda888
Added non-std verilog assume() statement
2015-02-26 18:47:39 +01:00
Clifford Wolf
27a918eadf
Merge branch 'master' of github.com:cliffordwolf/yosys
2015-02-25 23:01:54 +01:00
Clifford Wolf
331f8b8d0b
Bugfix in iopadmap
2015-02-25 23:01:42 +01:00
Clifford Wolf
3fe18c26cd
Added "keep_hierarchy" attribute
2015-02-25 12:46:00 +01:00
Clifford Wolf
9ae21263f0
Some cleanups in "clean"
2015-02-24 22:31:30 +01:00
Clifford Wolf
81fa4e81a6
Fixed compilation problems with gcc 4.6.3; use enum instead of const ints.
...
(original patch by Andrew Becker <andrew.becker@epfl.ch>)
2015-02-24 11:01:00 +01:00
Clifford Wolf
c4f383e452
Fixed "check -assert"
2015-02-22 16:29:44 +01:00
Clifford Wolf
d361d313e1
Added "check -assert" doc
2015-02-22 13:02:48 +01:00
Clifford Wolf
e8307cefd9
Added "check -assert"
2015-02-22 13:00:41 +01:00
Clifford Wolf
39d25b212c
Fixed "sat -initsteps" off-by-one bug
2015-02-22 12:42:05 +01:00
Clifford Wolf
fae0e75ace
Added "sat -stepsize" and "sat -tempinduct-step"
2015-02-21 22:52:49 +01:00
Clifford Wolf
b19c926af8
sat docu change
2015-02-21 22:03:54 +01:00
Clifford Wolf
9237fb924e
When "sat -tempinduct-baseonly -maxsteps N" reaches maxsteps it is a good thing.
2015-02-21 20:05:16 +01:00
Clifford Wolf
1688b9b464
Added "sat -tempinduct-baseonly -tempinduct-inductonly"
2015-02-21 17:53:22 +01:00
Clifford Wolf
dcbd00c101
Fixed basecase init for "sat -tempinduct"
2015-02-21 17:43:49 +01:00
Clifford Wolf
49dd9c713f
Fixed "flatten" for non-pre-derived modules
2015-02-21 15:01:13 +01:00
Clifford Wolf
4e6ca7760f
Replaced ezDefaultSAT with ezSatPtr
2015-02-21 12:15:41 +01:00
Clifford Wolf
f778a4081c
Catch constants assigned to cell outputs in "flatten"
2015-02-21 11:21:28 +01:00
Clifford Wolf
08c0fe164f
format fixes in "sat -dump_json"
2015-02-19 13:19:04 +01:00
Clifford Wolf
1ecee6c49c
Added "sat -dump_json" (WaveJSON format)
2015-02-19 10:53:40 +01:00
Clifford Wolf
20eb5cad4b
Changed "show" defaults for Win32
2015-02-19 09:11:38 +01:00
Clifford Wolf
f41378af8c
Fixed clang (svn trunk) warnings
2015-02-18 14:54:22 +01:00
Clifford Wolf
e4cf604ffd
Merge branch 'master' of github.com:cliffordwolf/yosys
2015-02-18 07:19:03 +01:00
Clifford Wolf
5f54be54b8
Added "select %xe %cie %coe"
2015-02-18 07:18:34 +01:00
Clifford Wolf
024aa559e2
wreduce help typo fix
2015-02-17 13:02:16 +01:00
Clifford Wolf
0748ef638d
Bugfix in wreduce
2015-02-16 09:08:00 +01:00
Clifford Wolf
0283703f9e
Added Viz to yosys.js
2015-02-15 22:53:41 +01:00
Clifford Wolf
40f021e136
Added "check -noinit"
2015-02-15 12:58:12 +01:00
Clifford Wolf
a54c994e2b
Cosmetic fixes in "hierarchy" for blackbox modules
2015-02-15 12:57:41 +01:00
Clifford Wolf
3216f9420e
More emscripten stuff, Added example app
2015-02-15 12:09:30 +01:00
Clifford Wolf
c6ae9ebb79
Fixed "stat" handling of blackbox modules
2015-02-14 22:36:34 +01:00
Clifford Wolf
e9368a1d7e
Various fixes for memories with offsets
2015-02-14 14:21:15 +01:00
Clifford Wolf
dcf2e24240
Added $meminit support to "memory" command
2015-02-14 12:55:03 +01:00
Clifford Wolf
910556560f
Added $meminit cell type
2015-02-14 10:23:03 +01:00
Clifford Wolf
a0a0594d1e
hotfix in "check" command
2015-02-13 14:40:49 +01:00
Clifford Wolf
04cb947d6a
Added "check" command
2015-02-13 14:34:51 +01:00
Clifford Wolf
d58c3eca3a
Some test related fixes
...
(incl. removal of three bad test cases)
2015-02-12 17:45:44 +01:00
Clifford Wolf
554a8df5e2
Added "proc_dlatch"
2015-02-12 16:56:01 +01:00
Clifford Wolf
87819c62fa
Less aggressive "share" defaults
2015-02-10 20:51:37 +01:00
Clifford Wolf
510deb3577
Added "scc -expect <N> -nofeedback"
2015-02-10 08:48:55 +01:00
Clifford Wolf
f889e3d385
Fixed iterator invalidation bug in "rename" command
2015-02-09 00:18:36 +01:00
Clifford Wolf
07afb14318
Fixed bug in "show -format .."
2015-02-08 23:29:54 +01:00
Clifford Wolf
bcd8a2fc56
Fixed eval_select_op() api
2015-02-08 19:06:16 +01:00
Clifford Wolf
09ee65a050
Added eval_select_args() and eval_select_op()
2015-02-08 18:56:06 +01:00
Clifford Wolf
5170b86108
Added equiv_add
2015-02-08 11:59:38 +01:00
Clifford Wolf
d5e30978e9
Added "select -read"
2015-02-06 10:01:22 +01:00
Clifford Wolf
a038787c9b
Added onehot attribute
2015-02-04 18:52:54 +01:00
Clifford Wolf
8805c24640
Fixed opt_clean performance bug
2015-02-04 16:34:06 +01:00
Clifford Wolf
a8f4a099b5
Using design->selected_modules() in opt_*
2015-02-03 23:45:01 +01:00
Clifford Wolf
6eb34038f4
Merge pull request #48 from rubund/master
...
Fixed typos found by lintian
2015-02-01 22:55:52 +01:00
Clifford Wolf
893fe87a33
Improved performance in equiv_simple
2015-02-01 22:50:48 +01:00
Ruben Undheim
49649d6ef0
Fixed typos found by lintian
2015-02-01 21:49:55 +01:00
Clifford Wolf
9abbeefe6e
Using selections in "ls" command
2015-02-01 00:13:19 +01:00
Clifford Wolf
8dfa105255
Bugfix in opt_const $eq -> buffer code
2015-01-31 23:25:32 +01:00
Clifford Wolf
1d92915a55
Fixed equiv_make for partially undriven nets (e.g. after "clean -purge")
2015-01-31 21:07:42 +01:00
Clifford Wolf
bc86b4a7e9
Added "equiv_induct -undef"
2015-01-31 13:58:04 +01:00
Clifford Wolf
e9cfc4a453
Added "equiv_simple -undef"
2015-01-31 13:06:41 +01:00
Clifford Wolf
f80f5b721d
Added "equiv_make -blacklist <file> -encfile <file>"
2015-01-31 12:08:20 +01:00
Clifford Wolf
bedd46338f
Added "fsm -encfile"
2015-01-30 22:46:53 +01:00
Clifford Wolf
9ebf803cbe
Improved an error message
2015-01-28 00:46:00 +01:00
Clifford Wolf
df64542288
Fixed bug in equiv_miter
2015-01-28 00:34:30 +01:00
Clifford Wolf
23e54bda81
Added "sat -show-ports"
2015-01-27 23:04:28 +00:00
Clifford Wolf
13b50bacfe
Rethrow with "catch(...) throw;"
2015-01-25 22:57:09 +01:00
Clifford Wolf
acfaeb8d34
Added equiv_remove
2015-01-25 14:20:22 +01:00
Clifford Wolf
66a6b86daa
Added equiv_miter
2015-01-25 14:00:49 +01:00
Clifford Wolf
2a9ad48eb6
Added ENABLE_NDEBUG makefile options
2015-01-24 12:16:46 +01:00
Clifford Wolf
75bbeb828a
Various equiv_* improvements
2015-01-24 00:32:24 +01:00
Clifford Wolf
43951099cf
Added dict/pool.sort()
2015-01-24 00:13:27 +01:00
Clifford Wolf
1cb4c925d0
Improvements in equiv_make, equiv_induct
2015-01-22 21:23:01 +01:00
Clifford Wolf
5707ba22c1
Improved xdot calling
2015-01-22 20:45:53 +01:00
Clifford Wolf
f6d94e8720
Added equiv_induct
2015-01-22 14:03:18 +01:00
Clifford Wolf
a6aa32e762
Various equiv_simple improvements
2015-01-22 13:42:04 +01:00
Clifford Wolf
0a225f8b27
Moved equiv stuff to passes/equiv/
2015-01-22 12:03:15 +01:00
Clifford Wolf
abf8398216
Progress in equiv_simple
2015-01-21 23:59:58 +00:00
Clifford Wolf
74e1de1fac
Fixed opt_muxtree performance bug
2015-01-21 16:44:07 +01:00
Clifford Wolf
5febbe3620
Added equiv_simple
2015-01-19 15:08:44 +01:00
Clifford Wolf
615c2e136e
Added equiv_status
2015-01-19 14:20:04 +01:00
Clifford Wolf
76c5d863c5
Added equiv_make command
2015-01-19 13:59:08 +01:00
Clifford Wolf
8d295730e5
Refactoring of memory_bram and xilinx brams
2015-01-18 19:05:29 +01:00
Clifford Wolf
f630868bc9
Improvements in opt_muxtree
2015-01-18 12:57:36 +01:00
Clifford Wolf
d3b35017f8
More opt_muxtree cleanups
2015-01-18 12:13:18 +01:00
Clifford Wolf
61192514e3
Various cleanups and improvements in opt_muxtree
2015-01-18 11:17:56 +01:00
Clifford Wolf
8658eed52a
Added support for memories to flatten (techmap)
2015-01-17 20:46:52 +01:00
Clifford Wolf
a95c229e12
Fixed a bug in opt_muxtree for "mux forests"
2015-01-17 13:56:53 +01:00
Clifford Wolf
3628ca989c
Improved opt_muxtree
2015-01-17 12:05:19 +01:00
Clifford Wolf
8ce8a230f4
Bugfix in dff2dffe
2015-01-16 17:51:17 +01:00
Clifford Wolf
2e36faeced
Added "abc -lut w1:w2"
2015-01-15 13:37:48 +01:00
Clifford Wolf
9065fb25cc
Fixed handling of foo.__TECHMAP_...
2015-01-15 13:36:57 +01:00
Clifford Wolf
8426884b40
Re-enabled mux->and/or transform (and fixed lm32 in yosys-bigsim)
2015-01-13 13:20:09 +01:00
Clifford Wolf
95f1eb9b87
Only enable code coverage counters on linux
2015-01-09 17:32:53 +01:00
Clifford Wolf
fd787609aa
disabled problematic mux -> and/or transform
2015-01-07 23:25:51 +01:00
Clifford Wolf
b26590f8ab
memory_bram hotfix for memories with width 1
2015-01-06 23:59:53 +01:00
Clifford Wolf
da72050107
removed old debug code
2015-01-06 16:08:04 +01:00
Clifford Wolf
9474928672
Towards Xilinx bram support
2015-01-06 15:26:33 +01:00
Clifford Wolf
4a0b3a5423
Various small improvements to synth_xilinx
2015-01-06 14:37:50 +01:00
Clifford Wolf
081e1a49f8
Towards Xilinx bram support
2015-01-06 14:26:51 +01:00
Clifford Wolf
462b22f44f
dict<> ref vs insert bugfix
2015-01-06 00:16:44 +01:00
Clifford Wolf
9ea2511fe8
Towards Xilinx bram support
2015-01-05 13:59:04 +01:00
Clifford Wolf
8898897f7b
Towards Xilinx bram support
2015-01-04 14:23:30 +01:00
Clifford Wolf
daae35319b
Added memory_bram "shuffle_enable" feature
2015-01-04 13:14:30 +01:00
Clifford Wolf
5d631f0ea7
Removed left over debug code from memory_bram
2015-01-04 11:46:04 +01:00
Clifford Wolf
0648e2874c
Fixed pattern matching in "hierarchy -generate"
2015-01-04 11:45:39 +01:00
Clifford Wolf
45918b8315
Added "memory -bram"
2015-01-03 17:40:20 +01:00
Clifford Wolf
a7fe87f888
Added memory_bram 'or_next_if_better' feature
2015-01-03 17:34:05 +01:00
Clifford Wolf
fd2c224c04
memory_bram transp support
2015-01-03 12:41:46 +01:00
Clifford Wolf
a7e43ae3d9
Progress in memory_bram
2015-01-03 10:57:01 +01:00
Clifford Wolf
90f4017703
Added proper clkpol support to memory_bram
2015-01-02 22:57:08 +01:00
Clifford Wolf
bbf89c4dc6
Progress in memory_bram
2015-01-02 13:59:47 +01:00
Clifford Wolf
36c20f2ede
Progress in memory_bram
2015-01-02 00:07:44 +01:00
Clifford Wolf
f29f4e7c83
Progress in memory_bram
2015-01-01 15:32:37 +01:00
Clifford Wolf
17c1c55473
Progress in memory_bram
2015-01-01 12:17:19 +01:00
Clifford Wolf
e62d838bd4
Removed SigSpec::extend_xx() api
2015-01-01 11:41:52 +01:00
Clifford Wolf
327a5d42b6
Progress in memory_bram
2014-12-31 22:50:08 +01:00
Clifford Wolf
94e6b70736
Added memory_bram (not functional yet)
2014-12-31 16:53:53 +01:00
Clifford Wolf
11c3b81c08
typo fix for "opt -fast"
2014-12-30 22:35:38 +01:00
Clifford Wolf
972faab1c8
Fixed a bug in "select %ci %co %x"
2014-12-30 20:15:18 +01:00
Clifford Wolf
4606addfef
Fixed typo in ABC command
2014-12-30 19:38:40 +01:00
Clifford Wolf
c64b1de11d
Fixed build with SMALL=1
2014-12-30 11:41:24 +01:00
Clifford Wolf
ed8f1b42fc
Fixed memory corruption in "splice" command
2014-12-29 20:23:22 +01:00
Clifford Wolf
29a555ec7e
Added statehash to ezSAT
2014-12-29 17:10:37 +01:00
Clifford Wolf
7a4d5d1c0f
Less verbose ABC output
2014-12-29 15:17:40 +01:00
Clifford Wolf
3ff0d04555
Cleanups in opt_clean
2014-12-29 05:11:06 +01:00
Clifford Wolf
7d843adef9
dict/pool changes in opt_clean
2014-12-29 04:06:52 +01:00
Clifford Wolf
cfe0817697
Converting "share" to dict<> and pool<> complete
2014-12-29 02:01:42 +01:00
Clifford Wolf
9ff3a9f30d
Switched most of "share" to dict<> and pool<>
2014-12-29 00:42:48 +01:00
Clifford Wolf
445686cba3
using dict and pool in opt_reduce
2014-12-28 21:27:05 +01:00
Clifford Wolf
951c72ba52
bugfix in opt_share
2014-12-28 21:26:36 +01:00
Clifford Wolf
3da46d3437
Renamed hashmap.h to hashlib.h, some related improvements
2014-12-28 17:51:16 +01:00
Clifford Wolf
6c8b0a5fd1
More dict/pool related changes
2014-12-27 12:02:57 +01:00
Clifford Wolf
66ab88d7b0
More hashtable finetuning
2014-12-27 03:04:50 +01:00
Clifford Wolf
ec4751e55c
Replaced std::unordered_set (nodict) with Yosys::pool
2014-12-26 21:59:41 +01:00
Clifford Wolf
9e6fb0b02c
Replaced std::unordered_map as implementation for Yosys::dict
2014-12-26 21:35:22 +01:00
Clifford Wolf
a6c96b986b
Added Yosys::{dict,nodict,vector} container types
2014-12-26 10:53:21 +01:00
Clifford Wolf
b748622a7f
Added "test_cell -muxdiv"
2014-12-25 19:22:39 +01:00
Clifford Wolf
7dece74fae
Added "test_cell -w" feature
2014-12-25 17:04:13 +01:00
Clifford Wolf
170788a3de
Fixed simplemap for $ne cells with output width > 1
2014-12-25 16:41:20 +01:00
Clifford Wolf
b6a7e21d2e
Fixed off-by-one bug in "hierarchy -check" for positional module args
2014-12-24 16:26:18 +01:00
Clifford Wolf
aad195b88c
Added "dfflibmap -prepare" help
2014-12-24 12:56:05 +01:00
Clifford Wolf
35f5aa300f
Added "dfflibmap -prepare"
2014-12-24 12:19:20 +01:00
Clifford Wolf
032ce573a3
Added "dff2dffe -direct" for direct gate mapping
2014-12-24 11:39:15 +01:00
Clifford Wolf
8c1a72c2a4
Added "dff2dffe -unmap"
2014-12-24 11:09:01 +01:00
Clifford Wolf
afcacd6437
Added support for gate-level cells in dff2dffe
2014-12-24 10:49:54 +01:00
Clifford Wolf
4aa9fbbf3f
Improvements in simplemap api, added $ne $nex $eq $eqx support
2014-12-24 10:49:24 +01:00
Clifford Wolf
edb3c9d0c4
Renamed extend() to extend_xx(), changed most users to extend_u0()
2014-12-24 09:51:17 +01:00
Clifford Wolf
48ca1ff9ef
Improved ABC clock domain partitioning
2014-12-23 14:08:38 +01:00
Clifford Wolf
5fe02b7965
Indenting fix in show.cc
2014-12-23 13:49:54 +01:00
Clifford Wolf
4f5b97954e
Added "show -colorattr"
2014-12-23 12:29:29 +01:00
Clifford Wolf
a216df0433
Added "abc -markgroups"
2014-12-23 12:29:02 +01:00
Clifford Wolf
76fa527492
Added support for multiple clock domains to "abc" pass
2014-12-21 16:52:05 +01:00
Clifford Wolf
25844b5683
Fixed "abc" pass for clk and enable signals driven by logic
2014-12-21 11:13:25 +01:00
Clifford Wolf
f7b323196f
Added DFFE support to "abc" pass
2014-12-20 00:44:03 +01:00
Clifford Wolf
bacd3699b3
Checking existence of ports in "hierarchy -check"
2014-12-19 18:47:19 +01:00
Clifford Wolf
032511fac8
Added functionality to dff2dffe pass
2014-12-08 15:38:58 +01:00
Clifford Wolf
97487fee32
Added skeleton dff2dffe pass
2014-12-08 14:10:52 +01:00
Clifford Wolf
f1764b4fe9
Added $dffe cell type
2014-12-08 10:50:19 +01:00
Clifford Wolf
51cfcd8331
Fixed bug in "hierarchy -top" with array of instances
2014-11-27 12:47:33 +01:00
Clifford Wolf
a112b10934
Introducing YS_OVERRIDE, YS_FINAL, YS_ATTRIBUTE, YS_NORETURN
2014-11-09 10:55:04 +01:00
Clifford Wolf
fe829bdbdc
Added log_warning() API
2014-11-09 10:44:23 +01:00
Clifford Wolf
d92fb5b35e
Added missing fixup_ports() calls to "rename" command
2014-11-08 12:38:48 +01:00
Clifford Wolf
420bc05627
Added "Nx" syntax to "show" command for repeating SigChunks
2014-11-08 10:58:57 +01:00
Clifford Wolf
546e8b5fe7
Improved TopoSort determinism
2014-11-07 15:21:03 +01:00
Clifford Wolf
99cdfb3110
Fixed typo in "log_cmd_error_exception"
2014-11-07 12:48:15 +01:00
Clifford Wolf
a346c0bf2b
Made "cover" a compile-time option (disabled by default)
2014-11-06 09:39:55 +01:00
Clifford Wolf
ab28491f27
Added "opt -full" alias for all more aggressive optimizations
2014-10-31 03:36:51 +01:00
Clifford Wolf
c5eb5e56b8
Re-introduced Yosys::readsome() helper function
...
(f.read() + f.gcount() made problems with lines > 16kB)
2014-10-23 10:58:36 +02:00
Clifford Wolf
bb631c6f5c
Also look for yosys-abc in parent dir on win32
2014-10-18 19:01:44 +02:00
Clifford Wolf
41db98ba31
Fixed typo in test_cell
2014-10-18 16:52:06 +01:00
Clifford Wolf
84ffe04075
Fixed various VS warnings
2014-10-18 15:20:38 +02:00
Clifford Wolf
468ae92374
Various win32 / vs build fixes
2014-10-17 14:01:47 +02:00
Clifford Wolf
973d376733
Added genfiles.zip to MXE "make dist"
2014-10-17 12:11:15 +02:00
Clifford Wolf
4df902637a
Various MXE build fixes
2014-10-17 12:04:40 +02:00
William Speirs
31267a1ae8
Header changes so it will compile on VS
2014-10-17 11:41:36 +02:00
Clifford Wolf
18cb8b4636
Don't be too smart with $dff cells with "init" attribute on out signal
2014-10-16 11:49:31 +02:00
Clifford Wolf
66eb254fc2
Some cleanups in opt_clean
2014-10-16 11:46:57 +02:00
Clifford Wolf
c3e9922b5d
Replaced readsome() with read() and gcount()
2014-10-15 01:12:53 +02:00
William Speirs
e5b8390f44
Changed from "and" to "&&"
2014-10-15 00:59:22 +02:00
William Speirs
6433203b39
Wrapped init in std::set constructor
2014-10-15 00:58:05 +02:00
Clifford Wolf
c21c9dab1e
Removed CHECK() macro from libparse.cc (was using non-std c features)
2014-10-13 17:22:06 +02:00
Clifford Wolf
0913e968f5
More win32/abc fixes
2014-10-12 14:48:19 +02:00
Clifford Wolf
0b9282a779
Added make_temp_{file,dir}() and remove_directory() APIs
2014-10-12 12:11:57 +02:00
Clifford Wolf
9b4d171e37
Using stringf() instead of asprintf() in "abc" pass
2014-10-12 11:17:53 +02:00
Clifford Wolf
b1596bc0e7
Added run_command() api to replace system() and popen()
2014-10-12 10:57:15 +02:00
Clifford Wolf
d2b8b48bf3
Renamed "log.cc" to "logcmd.cc" so there aren't two "log.cc" in the source tree
2014-10-11 12:13:46 +02:00
Clifford Wolf
35fbc0b35f
Do not the 'z' modifier in format string (another win32 fix)
2014-10-11 11:42:08 +02:00
Clifford Wolf
8263f6a74a
Fixed win32 troubles with f.readsome()
2014-10-11 11:36:22 +02:00
Clifford Wolf
51b1824979
Disabled "cover -d" on win32
2014-10-11 10:49:43 +02:00
Clifford Wolf
54bf3a95dd
More Win32 build fixes
2014-10-10 18:34:19 +02:00
Clifford Wolf
ee5165c6e4
Moved patmatch() to yosys.cc
2014-10-10 18:20:17 +02:00
Clifford Wolf
774933a0d8
Replaced fnmatch() with patmatch()
2014-10-10 18:02:17 +02:00
Clifford Wolf
bbd808072b
Added format __attribute__ to stringf()
2014-10-10 17:22:08 +02:00
Clifford Wolf
7cb0d3aa1a
Renamed TRUE/FALSE to CONST_TRUE/CONST_FALSE because of name collision on Win32
2014-10-10 17:07:24 +02:00
Clifford Wolf
4569a747f8
Renamed SIZE() to GetSize() because of name collision on Win32
2014-10-10 17:07:24 +02:00
Clifford Wolf
fea11f0fa4
Added API for generic cell cost calculations
2014-10-09 13:59:26 +02:00
Clifford Wolf
ccf7b2e342
Added mxe-based cross build for win32
2014-10-09 10:50:44 +02:00
Clifford Wolf
696d7ed40e
Fixes in "hilomap" help message
2014-10-08 21:38:37 +02:00
Clifford Wolf
9dea161321
sort cell types in "stat" output by name
2014-10-03 19:21:04 +02:00
Clifford Wolf
c5c7066ea6
sat encoding for exclusive $pmux ctrl inputs in "share" pass
2014-10-03 19:01:24 +02:00
Clifford Wolf
3e4b0cac8d
added resource sharing of $macc cells
2014-10-03 12:58:40 +02:00
Clifford Wolf
c3e779a65f
Added $_BUF_ cell type
2014-10-03 10:12:28 +02:00
Clifford Wolf
600c6cb013
remove buffers in opt_clean
2014-10-03 10:04:15 +02:00
Clifford Wolf
7019bc00e4
resource sharing of $alu cells
2014-10-03 09:55:50 +02:00
Clifford Wolf
2ee03f5da4
set "keep" on modules with $assert cells in "hierarchy"
2014-09-30 19:16:40 +02:00
Clifford Wolf
0b8cfbc6fd
Added support for "keep" on modules
2014-09-29 12:51:54 +02:00
Clifford Wolf
f9a307a50b
namespace Yosys
2014-09-27 16:17:53 +02:00
Clifford Wolf
13117bb346
Re-enabled assert for new logic loops in "share" pass
2014-09-21 19:44:08 +02:00
Clifford Wolf
96e821dc6c
Various improvements regarding logic loops in "share" results
2014-09-21 19:36:56 +02:00
Clifford Wolf
d6e2ace95b
Logic loop bugfix for "share" pass
2014-09-21 15:13:44 +02:00
Clifford Wolf
b28be0759f
Added "share -limit"
2014-09-21 15:13:06 +02:00
Clifford Wolf
a6c08b40fe
Still loop bug in "share": changed assert to warning
2014-09-21 14:51:07 +02:00
Clifford Wolf
8d60754aef
Do not introduce new logic loops in "share"
2014-09-21 13:52:39 +02:00
Clifford Wolf
edf11c635a
Assert on new logic loops in "share" pass
2014-09-21 12:57:33 +02:00
Clifford Wolf
a7758ef953
Added "test_abcloop" command
2014-09-19 15:51:34 +02:00
Clifford Wolf
5827826098
Small improvements in "abc" command handle_loops() function
2014-09-19 14:05:41 +02:00
Clifford Wolf
3aa003c8e9
Using "NOT" instead of "INV" as cell name in default abc genlib file
2014-09-19 13:15:31 +02:00
Clifford Wolf
f7bb8f244b
Alphabetically sort port names in "show" output
2014-09-19 11:13:10 +02:00
Clifford Wolf
f56b92818b
Do not run "scorr" in "abc -fast"
2014-09-18 19:00:21 +02:00
Clifford Wolf
815fab9d71
Added "abc -fast"
2014-09-18 12:57:37 +02:00
Clifford Wolf
9ae559b990
Fixed $_NOR vs. $_NOR_ typo in abc.cc
2014-09-16 12:45:05 +02:00
Clifford Wolf
ae02d9cb9a
Fixed $memwr/$memrd order in memory_dff
2014-09-16 12:40:58 +02:00
Clifford Wolf
b86410b2ab
More aggressive $macc merging in alumacc
2014-09-15 12:42:11 +02:00
Clifford Wolf
b470c480e9
Added the obvious optimizations to alumacc $macc generator
2014-09-15 12:22:03 +02:00
Clifford Wolf
fcbda07411
Improved maccmap tree bit packing
2014-09-15 12:00:19 +02:00
Clifford Wolf
2cbdbaad1f
Fixed wreduce $shiftx handling
2014-09-15 11:29:09 +02:00
Clifford Wolf
7e156a5419
Fixed techmap_wrap for techmap_celltype
2014-09-14 15:34:36 +02:00
Clifford Wolf
014bb34e0e
Various fixes/cleanups in alumacc and maccmap
2014-09-14 14:49:53 +02:00
Clifford Wolf
124e759280
Added techmap_wrap attribute
2014-09-14 14:49:26 +02:00
Clifford Wolf
b34ca15185
alumacc fix for $pos cells
2014-09-14 14:00:14 +02:00
Clifford Wolf
0df1d9ad72
Extract $alu cells in alumacc
2014-09-14 13:23:44 +02:00
Clifford Wolf
7b16c63101
Merge $macc cells in alumacc pass
2014-09-14 11:21:37 +02:00
Clifford Wolf
0b72f0acb1
Basic $macc extract in alumacc
2014-09-14 10:45:28 +02:00
Clifford Wolf
ff157fb74f
alumacc skeleton
2014-09-14 10:02:00 +02:00
Clifford Wolf
aab0e3bf70
Cleanup in wreduce
2014-09-14 10:01:30 +02:00
Clifford Wolf
af0c8873bb
Added $lcu cell type
2014-09-08 13:31:04 +02:00
Clifford Wolf
d46bac3305
Added "$fa" cell type
2014-09-08 12:15:39 +02:00
Clifford Wolf
1a88e47396
Trim msb/lsb zero bits from full adder in maccmap
2014-09-08 11:21:58 +02:00
Clifford Wolf
6747a7047e
Added "test_cell -const"
2014-09-08 11:12:39 +02:00
Clifford Wolf
c50b841b29
Added 'techmap_maccmap' techmap attribute
2014-09-07 18:23:37 +02:00
Clifford Wolf
015dcdc84c
Added "maccmap" command
2014-09-07 18:23:04 +02:00
Clifford Wolf
15b3c54fea
Added "test_cell -nosat"
2014-09-07 17:05:41 +02:00
Clifford Wolf
9329a76818
Various bug fixes (related to $macc model testing)
2014-09-06 20:30:46 +02:00
Clifford Wolf
fa64942018
Added $macc SAT model
2014-09-06 19:44:11 +02:00
Clifford Wolf
b847ec8a0b
Added $macc cell type
2014-09-06 15:47:46 +02:00
Clifford Wolf
34af6a1303
Merge branch 'master' of github.com:cliffordwolf/yosys
2014-09-06 11:46:44 +02:00
Clifford Wolf
e1743b3bac
Added "test_cell -script"
2014-09-06 11:46:07 +02:00
Ruben Undheim
79cbf9067c
Corrected spelling mistakes found by lintian
2014-09-06 08:47:06 +02:00
Clifford Wolf
f5a40e7043
Fixed "opt_const -fine" for $pos cells
2014-09-04 08:55:58 +02:00
Clifford Wolf
8927aa6148
Removed $bu0 cell type
2014-09-04 02:07:52 +02:00
Clifford Wolf
5733f4a39d
Fixed "test_cells -vlog"
2014-09-03 13:43:37 +02:00
Clifford Wolf
f1869667ca
Improvements in "test_cell -vlog"
2014-09-02 23:21:15 +02:00
Clifford Wolf
66bf2bb92e
Added test_cell -vlog
2014-09-02 22:49:43 +02:00
Clifford Wolf
acd7a99aef
Added SAT testing to test_cell eval stage
2014-09-02 17:28:13 +02:00
Clifford Wolf
37fe7c7bdf
Removed references to yosys-svgviewer from docs
2014-09-02 04:03:06 +02:00
Clifford Wolf
9f00a0cd2d
Using "xdot" instead of "yosys-svgviewer" in show command
2014-09-02 03:28:46 +02:00
Clifford Wolf
630befdf6d
Added $alu support to test_cell
2014-09-01 16:36:04 +02:00
Clifford Wolf
c7f81e4e49
Added "test_cell -simlib -v"
2014-09-01 15:37:21 +02:00
Clifford Wolf
826fdb34d8
Added "techmap -autoproc"
2014-09-01 15:36:29 +02:00
Clifford Wolf
27a1bfbec6
Fixes in old SAT example.ys
2014-09-01 11:45:47 +02:00
Clifford Wolf
d5148f2e01
Moved "share" and "wreduce" to passes/opt/
2014-09-01 11:45:26 +02:00
Clifford Wolf
e07698818d
Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::data
2014-09-01 11:36:02 +02:00
Clifford Wolf
e3664066d5
Added eval testing to test_cell
2014-08-31 18:08:42 +02:00
Clifford Wolf
8649b57b6f
Added $lut support in test_cell, techmap, satgen
2014-08-31 17:43:31 +02:00
Clifford Wolf
2a1b08aeb3
Added design->scratchpad
2014-08-30 19:37:12 +02:00
Clifford Wolf
6ff46323a3
Improved write address decoder generation memory_map
2014-08-30 18:18:15 +02:00
Clifford Wolf
66763fad4e
Using worker class in memory_map
2014-08-30 17:39:08 +02:00
Clifford Wolf
3a7d5d188d
Don't change existing binary FSM encoding if it is already optimal
2014-08-30 14:43:06 +02:00
Clifford Wolf
f910481f35
Using $pmux info in fsm_extract to optimize transition ctrl_in patterns
2014-08-30 14:34:49 +02:00
Clifford Wolf
ab019b0bd5
Improved handling of $pmux cells in fsm_extract
2014-08-30 14:11:57 +02:00
Clifford Wolf
d148b0af0d
Fixed inserting of Q-inverters in dfflibmap
2014-08-27 19:44:12 +02:00
Clifford Wolf
084685f480
Implemented "rename -enumerate -pattern"
2014-08-26 12:51:08 +02:00
Clifford Wolf
7bbbe3580d
Optimize shift ops with constant rhs in opt_const
2014-08-24 17:08:43 +02:00
Clifford Wolf
641501203c
Added some additional log messages to opt_const
2014-08-24 17:08:43 +02:00
Clifford Wolf
9c5a63c52c
azonenberg: Make dump_vcd save model when temporal induction fails due to step limit
2014-08-24 13:27:40 +02:00
Clifford Wolf
c642dd0b3e
Only call proc_share_dirname() in techmap when necessary
2014-08-23 15:32:00 +02:00
Clifford Wolf
19cff41eb4
Changed frontend-api from FILE to std::istream
2014-08-23 15:03:55 +02:00
Clifford Wolf
5dce303a2a
Changed backend-api from FILE to std::ostream
2014-08-23 13:54:21 +02:00
Clifford Wolf
fff12c719f
Added "stat -width"
2014-08-22 17:20:28 +02:00
Clifford Wolf
98442e019d
Added emscripten (emcc) support to build system and some build fixes
2014-08-22 16:20:22 +02:00
Clifford Wolf
a3494fa9ed
Added "plugin" command
2014-08-22 14:00:11 +02:00
Clifford Wolf
410d043dd8
Renamed toposort.h to utils.h
2014-08-17 00:55:35 +02:00
Clifford Wolf
7f734ecc09
Added module->uniquify()
2014-08-16 23:50:36 +02:00
Clifford Wolf
3b9157f9a6
Added "test_cell -s <seed>"
2014-08-16 19:44:31 +02:00
Clifford Wolf
47c2637a96
Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_
2014-08-16 18:29:39 +02:00
Clifford Wolf
eb17fbade5
Added "opt -fast"
2014-08-16 15:34:15 +02:00
Clifford Wolf
674f421b47
Bugfix in iopadmap
2014-08-15 14:29:42 +02:00
Clifford Wolf
b64b38eea2
Renamed $lut ports to follow A-Y naming scheme
2014-08-15 14:18:40 +02:00
Clifford Wolf
f092b50148
Renamed $_INV_ cell type to $_NOT_
2014-08-15 14:11:40 +02:00
Clifford Wolf
ca87116449
More idstring sort_by_* helpers and fixed tpl ordering in techmap
2014-08-15 02:40:46 +02:00
Clifford Wolf
d320e75087
document "techmap -map %<design-name>"
2014-08-15 02:01:30 +02:00
Clifford Wolf
1bf7a18fec
Added module->ports
2014-08-14 16:22:52 +02:00
Clifford Wolf
13f2f36884
RIP $safe_pmux
2014-08-14 11:39:46 +02:00
Clifford Wolf
28cf48e31f
Some improvements in FSM mapping and recoding
2014-08-14 11:22:45 +02:00
Clifford Wolf
996c06f64d
Added "abc -D" for setting delay target
2014-08-14 11:05:25 +02:00
Clifford Wolf
28bc7aeb93
Filter ANSI escape sequences from ABC output
2014-08-13 13:40:29 +02:00
Clifford Wolf
9d353fc543
Fixed handling of constant-true branches in proc_clean
2014-08-12 17:35:22 +02:00
Clifford Wolf
788bd02f97
Fixed FSM mapping for multiple reset-like signals
2014-08-10 12:04:02 +02:00
Clifford Wolf
9d4362990f
Fixed "share" for complex scenarios with never-active cells
2014-08-09 17:07:20 +02:00
Clifford Wolf
b9811d5aff
Do not share any $reduce_* cells (its complicated and not worth it anyways)
2014-08-09 15:40:25 +02:00
Clifford Wolf
2faef89738
Some improvements in fsm_opt and fsm_map for FSM with unreachable states
2014-08-09 14:49:51 +02:00
Clifford Wolf
58ac605470
Another fsm_extract bugfix
2014-08-08 14:56:04 +02:00
Clifford Wolf
7067c43ec0
Fixed "fsm -export"
2014-08-08 14:56:03 +02:00
Clifford Wolf
cb6ca08a53
Fixed sharing of reduce operator
2014-08-08 14:24:09 +02:00
Clifford Wolf
7c94024fc3
Fixed fsm_extract for wreduced muxes
2014-08-08 13:47:20 +02:00
Clifford Wolf
622ebab671
Added "sat -prove-skip"
2014-08-08 13:11:54 +02:00
Clifford Wolf
0b8b8d41eb
Fixed build with gcc-4.6
2014-08-07 22:37:01 +02:00
Clifford Wolf
c55eb8f8a6
Use "-keepdc" in "miter -equiv -flatten"
2014-08-07 16:42:35 +02:00
Clifford Wolf
b4f10e342c
Various improvements in memory_dff pass
2014-08-06 14:31:38 +02:00
Clifford Wolf
2501abe1ee
Various fixes and improvements in wreduce pass
2014-08-05 19:01:41 +02:00
Clifford Wolf
5b3dc07b9a
Removed old "constmap" from wreduce code
2014-08-05 16:53:53 +02:00
Clifford Wolf
523df73145
Added support for truncating of wires to wreduce pass
2014-08-05 14:47:03 +02:00
Clifford Wolf
d3b1a29708
Cleanups and improvements in wreduce pass
2014-08-05 13:11:04 +02:00
Clifford Wolf
1c182cedb7
Added mux support to wreduce command
2014-08-05 12:49:53 +02:00
Clifford Wolf
0bb6942218
Added "show -signed"
2014-08-04 15:40:08 +02:00
Clifford Wolf
ebbbe7fc83
Added RTLIL::IdString::in(...)
2014-08-04 15:40:07 +02:00
Clifford Wolf
c7f99be3be
Fixed "share" for memory read ports
2014-08-03 20:22:33 +02:00
Clifford Wolf
027376515a
Progress in "wreduce" pass
2014-08-03 20:02:42 +02:00
Clifford Wolf
0b02f6ca30
Added "wreduce" command (work in progress)
2014-08-03 15:02:05 +02:00
Clifford Wolf
014a41fcf3
Implemented recursive techmap
2014-08-03 12:40:43 +02:00
Clifford Wolf
9bb5298c10
Fixes in show command (related to new IdString)
2014-08-03 12:40:23 +02:00
Clifford Wolf
08ec33a5e5
Implemented simplemap support for "techmap -extern"
2014-08-02 21:55:13 +02:00
Clifford Wolf
b6acbc82e6
Bugfix in "techmap -extern"
2014-08-02 20:54:30 +02:00
Clifford Wolf
8e7361f128
Removed at() method from RTLIL::IdString
2014-08-02 19:08:02 +02:00
Clifford Wolf
04727c7e0f
No implicit conversion from IdString to anything else
2014-08-02 18:58:40 +02:00
Clifford Wolf
768eb846c4
More bugfixes related to new RTLIL::IdString
2014-08-02 18:14:21 +02:00
Clifford Wolf
8fd1c269ac
Fixed a performance bug in opt_reduce
2014-08-02 15:12:16 +02:00
Clifford Wolf
b9bd22b8c8
More cleanups related to RTLIL::IdString usage
2014-08-02 13:19:57 +02:00
Clifford Wolf
14412e6c95
Preparations for RTLIL::IdString redesign: cleanup of existing code
2014-08-02 00:45:25 +02:00
Clifford Wolf
bd74ed7da4
Replaced sha1 implementation
2014-08-01 19:01:10 +02:00
Clifford Wolf
d13eb7e099
Added ModIndex helper class, some changes to RTLIL::Monitor
2014-08-01 17:14:32 +02:00
Clifford Wolf
03ef9a75c6
Added "test_autotb -n <num_iter>" option
2014-08-01 03:55:51 +02:00
Clifford Wolf
32a1cc3efd
Renamed modwalker.h to modtools.h
2014-07-31 23:30:18 +02:00
Clifford Wolf
cdae8abe16
Renamed port access function on RTLIL::Cell, added param access functions
2014-07-31 16:38:54 +02:00
Clifford Wolf
b5a9e51b96
Added "trace" command
2014-07-31 15:02:16 +02:00
Clifford Wolf
e6d33513a5
Added module->design and cell->module, wire->module pointers
2014-07-31 14:11:39 +02:00
Clifford Wolf
1cb25c05b3
Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
2014-07-31 13:19:47 +02:00
Clifford Wolf
1202f7aa4b
Renamed "stdcells.v" to "techmap.v"
2014-07-31 02:32:00 +02:00
Clifford Wolf
6ca0c569d9
Added "techmap -assert"
2014-07-31 02:21:41 +02:00
Clifford Wolf
2541489105
Added techmap CONSTMAP feature
2014-07-30 22:04:30 +02:00
Clifford Wolf
6400ae3648
Added write_file command
2014-07-30 19:59:29 +02:00
Clifford Wolf
ceecf5b153
Improvements in test_cell
2014-07-30 18:49:12 +02:00
Clifford Wolf
273383692a
Added "test_cell" command
2014-07-29 22:07:41 +02:00
Clifford Wolf
e6df25bf74
Renamed "write_autotest" to "test_autotb" and moved to passes/tests/
2014-07-29 21:12:50 +02:00
Clifford Wolf
77e2d39cd0
Allow "hierarchy -generate" for $__ cells
2014-07-29 16:35:13 +02:00
Clifford Wolf
03c96f9ce7
Added "techmap -map %{design-name}"
2014-07-29 16:35:13 +02:00
Clifford Wolf
397b00252d
Added $shift and $shiftx cell types (needed for correct part select behavior)
2014-07-29 16:35:13 +02:00
Clifford Wolf
7bd2d1064f
Using log_assert() instead of assert()
2014-07-28 11:27:48 +02:00
Clifford Wolf
8b0f50792c
Added techmap -extern
2014-07-27 21:31:18 +02:00
Clifford Wolf
5da343b7de
Added topological sorting to techmap
2014-07-27 16:43:39 +02:00
Clifford Wolf
0c86d6106c
Added SigPool::check(bit)
2014-07-27 15:38:02 +02:00
Clifford Wolf
77a1462f2d
Fixed bug in opt_clean
2014-07-27 15:13:29 +02:00
Clifford Wolf
d07a871d35
Improved performance of opt_const on large modules
2014-07-27 14:50:25 +02:00
Clifford Wolf
dbb3556e3f
Fixed a bug in opt_clean and some RTLIL API usage cleanups
2014-07-27 13:19:05 +02:00
Clifford Wolf
d878fcbdc7
Added log_cmd_error_expection
2014-07-27 12:05:50 +02:00
Clifford Wolf
49f72421d5
Using new obj iterator API in a few places
2014-07-27 11:32:42 +02:00
Clifford Wolf
10e5791c5e
Refactoring: Renamed RTLIL::Design::modules to modules_
2014-07-27 11:18:30 +02:00
Clifford Wolf
4c4b602156
Refactoring: Renamed RTLIL::Module::cells to cells_
2014-07-27 01:51:45 +02:00
Clifford Wolf
f9946232ad
Refactoring: Renamed RTLIL::Module::wires to wires_
2014-07-27 01:49:51 +02:00
Clifford Wolf
d68c993ed2
Changed more code to the new RTLIL::Wire constructors
2014-07-26 21:30:38 +02:00
Clifford Wolf
946ddff9ce
Changed a lot of code to the new RTLIL::Wire constructors
2014-07-26 20:12:50 +02:00
Clifford Wolf
3f4e3ca8ad
More RTLIL::Cell API usage cleanups
2014-07-26 16:14:02 +02:00
Clifford Wolf
97a59851a6
Added RTLIL::Cell::has(portname)
2014-07-26 16:11:28 +02:00
Clifford Wolf
f8fdc47d33
Manual fixes for new cell connections API
2014-07-26 15:58:23 +02:00
Clifford Wolf
b7dda72302
Changed users of cell->connections_ to the new API (sed command)
...
git grep -l 'connections_' | xargs sed -i -r -e '
s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
s/(->|\.)connections_.push_back/\1connect/g;
s/(->|\.)connections_/\1connections()/g;'
2014-07-26 15:58:23 +02:00
Clifford Wolf
cc4f10883b
Renamed RTLIL::{Module,Cell}::connections to connections_
2014-07-26 11:58:03 +02:00
Clifford Wolf
4755e14e7b
Added copy-constructor-like module->addCell(name, other) method
2014-07-26 00:38:44 +02:00
Clifford Wolf
2bec47a404
Use only module->addCell() and module->remove() to create and delete cells
2014-07-25 17:56:19 +02:00
Clifford Wolf
5826670009
Various RTLIL::SigSpec related code cleanups
2014-07-25 14:25:42 +02:00
Clifford Wolf
0520bfea89
Fixed memory corruption in "opt_reduce" pass
2014-07-25 12:49:51 +02:00
Clifford Wolf
c4e4f79a2a
Disabled cover() for non-linux builds
2014-07-25 12:27:36 +02:00
Clifford Wolf
91bf0c90c8
Improvements in "cover" command
2014-07-25 12:04:40 +02:00
Clifford Wolf
6aa792c864
Replaced more old SigChunk programming patterns
2014-07-24 23:10:58 +02:00
Clifford Wolf
9962384d3e
Added cover() calls to opt_const
2014-07-24 20:47:18 +02:00
Clifford Wolf
45b4154b37
Added "make SMALL=1"
2014-07-24 19:03:57 +02:00
Clifford Wolf
b17d6531c8
Added "make PRETTY=1"
2014-07-24 17:15:01 +02:00
Clifford Wolf
2f54345cff
Added "cover" command
2014-07-24 16:14:19 +02:00
Clifford Wolf
20a7965f61
Various small fixes (from gcc compiler warnings)
2014-07-23 20:45:27 +02:00
Clifford Wolf
c094c53de8
Removed RTLIL::SigSpec::optimize()
2014-07-23 20:32:28 +02:00
Clifford Wolf
a62c21c9c6
Removed RTLIL::SigSpec::expand() method
2014-07-23 19:34:51 +02:00
Clifford Wolf
4e802eb7f6
Fixed all users of SigSpec::chunks_rw() and removed it
2014-07-23 15:36:09 +02:00
Clifford Wolf
ec923652e2
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3
2014-07-23 09:52:55 +02:00
Clifford Wolf
a8d3a68971
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3
2014-07-23 09:49:43 +02:00
Clifford Wolf
260c19ec5a
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3
2014-07-23 09:34:47 +02:00
Clifford Wolf
4a6d234ec7
SigSpec refactoring: cleanup of old SigSpec usage in fsm_* commands
2014-07-22 23:11:36 +02:00
Clifford Wolf
65a939cb27
Fixed memory corruption with new SigSpec API in proc_mux
2014-07-22 22:54:39 +02:00
Clifford Wolf
e7e30f1c86
fixed memory leak in fsm_opt
2014-07-22 22:52:57 +02:00
Clifford Wolf
28b3fd05fa
SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw()
2014-07-22 20:58:44 +02:00
Clifford Wolf
4b4048bc5f
SigSpec refactoring: using the accessor functions everywhere
2014-07-22 20:39:37 +02:00
Clifford Wolf
a233762a81
SigSpec refactoring: renamed chunks and width to __chunks and __width
2014-07-22 20:39:37 +02:00
Clifford Wolf
137dbf3cf7
Added "opt_const -keepdc"
2014-07-21 21:38:55 +02:00
Clifford Wolf
1873480ca5
Added mul to mux conversion to "opt_const -fine"
2014-07-21 17:19:50 +02:00
Clifford Wolf
1241a9fd50
Added "opt_const -fine" and "opt_reduce -fine"
2014-07-21 16:34:16 +02:00
Clifford Wolf
e035f1d886
Added opt_const support for simple identities
2014-07-21 14:41:02 +02:00
Clifford Wolf
361e0d62ff
Replaced depricated NEW_WIRE macro with module->addWire() calls
2014-07-21 12:42:02 +02:00
Clifford Wolf
1d88f1cf9f
Removed deprecated module->new_wire()
2014-07-21 12:35:06 +02:00
Clifford Wolf
3cb61d03f8
Wider range of cell types supported in "share" pass
2014-07-21 12:18:29 +02:00
Clifford Wolf
b49beab1f3
Use ezSAT::non_incremental() in "share" pass
2014-07-21 02:08:38 +02:00
Clifford Wolf
04fcb07213
Added support for resource sharing in mux control logic
2014-07-20 20:44:14 +02:00
Clifford Wolf
1ce5e83555
Added "select -assert-count"
2014-07-20 20:15:49 +02:00
Clifford Wolf
e9506bb2da
Supercell creation for $div/$mod worked all along, fixed test benches
2014-07-20 18:54:06 +02:00
Clifford Wolf
ff28029fdb
Fixed creation of shift supercells in "share" pass
2014-07-20 17:06:36 +02:00
Clifford Wolf
4c38ec1cc8
Added "miter -equiv -flatten"
2014-07-20 15:33:07 +02:00
Clifford Wolf
8d04ca7d22
Added call_on_selection() and call_on_module() API
2014-07-20 15:33:06 +02:00
Clifford Wolf
5b3ee7a072
Added "share" supercell creation
2014-07-20 15:01:17 +02:00
Clifford Wolf
7b98e46ac3
Added removing of always inactive cells to "share" pass
2014-07-20 13:24:36 +02:00
Clifford Wolf
8819493db4
Progress in "share" pass
2014-07-20 11:04:52 +02:00
Clifford Wolf
15fd615da5
Progress in "share" pass
2014-07-20 03:03:04 +02:00
Clifford Wolf
2278995bd8
Started to implement real resource sharing
2014-07-19 20:54:32 +02:00
Clifford Wolf
efd9604dfb
Improved memory_share log messages
2014-07-19 15:46:11 +02:00
Clifford Wolf
e0a819dbe5
More verbose memory_share help message
2014-07-19 15:34:14 +02:00
Clifford Wolf
297a0962ea
Added SAT-based write-port sharing to memory_share
2014-07-19 15:33:55 +02:00
Clifford Wolf
26f982ac0b
Fixed bug in memory_share feedback-to-en code
2014-07-19 15:32:14 +02:00
Clifford Wolf
e441f07d89
Added translation from read-feedback to en-signals in memory_share
2014-07-18 16:46:40 +02:00
Clifford Wolf
44f13aff92
Improved seeding of color rng in show command
2014-07-18 16:44:45 +02:00
Clifford Wolf
a341931972
Only create collision detect logic in memory_share if necessary
2014-07-18 14:32:40 +02:00
Clifford Wolf
ab4b26679f
Added memory_share
2014-07-18 13:16:56 +02:00
Clifford Wolf
309ae98246
Apply opt_reduce WR_EN opts to the whole mux tree driving the WR_EN port
2014-07-18 10:28:45 +02:00
Clifford Wolf
1b00861d0a
Improved opt_reduce handling of mem wr_en mux bits
2014-07-17 12:12:04 +02:00
Clifford Wolf
b76bf05cda
Added support for "blackbox" attribute to iopadmap
2014-07-17 08:59:07 +02:00
Clifford Wolf
64a6906cc4
Added support for "blackbox" attribute to flatten/techmap
2014-07-17 08:58:51 +02:00
Clifford Wolf
d678b6533d
improved opt_reduce for $mem/$memwr WR_EN multiplexers
2014-07-16 14:08:51 +02:00
Clifford Wolf
765f172211
Changes to "memory" pass for new $memwr/$mem WR_EN interface
2014-07-16 12:49:50 +02:00
Clifford Wolf
3b52121d32
now ignore init attributes on non-register wires in sat command
2014-07-05 11:18:38 +02:00
Clifford Wolf
1c85584fe5
Do not create $dffsr cells with no-op resets in proc_dff
2014-06-19 12:29:29 +02:00
Clifford Wolf
22a998903b
Added %D and %c select commands
2014-06-14 16:19:32 +02:00
Clifford Wolf
744e518467
fixed cell array handling of positional arguments
2014-06-07 12:17:11 +02:00
Clifford Wolf
e275e8eef9
Add support for cell arrays
2014-06-07 11:48:50 +02:00
Clifford Wolf
7020f7fc13
added tee cmd
2014-06-03 09:23:31 +02:00
Clifford Wolf
68c99bf734
Fixed log messages in memory_dff
2014-06-01 11:32:27 +02:00
Johann Glaser
278085fa01
added log_header to miter and expose pass, show cell type for exposed ports
2014-05-28 18:05:38 +02:00
Johann Glaser
684c85902d
be more verbose when techmap yielded processes
2014-05-26 17:13:41 +02:00
Clifford Wolf
68c059565a
Fixed bug in opt_reduce (see vloghammer issue_044)
2014-05-12 12:45:47 +02:00
Clifford Wolf
f69b5800c9
fixed syntax error in dot file created by "show" command
2014-05-10 16:22:56 +02:00
Clifford Wolf
9a34486bfb
Fixed performance problem in opt_mux with nets driven by many conflicting drivers
2014-03-19 10:05:01 +01:00
Clifford Wolf
34e54cda5b
Small improvement in SAT log messages
2014-03-13 13:12:49 +01:00
Clifford Wolf
fad8558eb5
Merged OSX fixes from Siesh1oo with some modifications
2014-03-13 12:48:10 +01:00
Siesh1oo
8127d5e8c3
- kernel/register.h, kernel/driver.cc: refactor rewrite_yosys_exe()/get_share_file_name() to portable proc_self_dirname()/proc_share_dirname().
...
This refactoring improves robustness and allows OSX support with only 7 new lines of code, and easy extension for other systems.
- passes/abc/abc.cc, passes/cmds/show.cc, passes/techmap/techmap.cc: use new, refactored semantics.
2014-03-12 23:17:14 +01:00
Clifford Wolf
9087ece97c
OSX compatible creation of stdcells.inc, using code from github.com/Siesh1oo/yosys
...
(see https://github.com/cliffordwolf/yosys/pull/28 )
2014-03-11 14:52:37 +01:00
Clifford Wolf
91704a7853
Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys
...
(see https://github.com/cliffordwolf/yosys/pull/28 )
2014-03-11 14:24:24 +01:00
Clifford Wolf
fa75c8286e
Fixed memory corruption in passes/abc/blifparse.cc
2014-03-11 13:09:01 +01:00
Clifford Wolf
fcae92868d
Fixed dumping of timing() { .. } block in libparse
2014-03-09 15:16:07 +01:00
Clifford Wolf
22aabe05c9
Verbose reading of liberty and constr files in ABC pass
2014-03-09 15:15:38 +01:00
Clifford Wolf
e3b11ea2d6
Fixed bug in freduce command
2014-03-07 18:44:23 +01:00
Clifford Wolf
6f8865d81a
Some minor code cleanups in freduce command
2014-03-07 18:29:04 +01:00
Clifford Wolf
54d74cf616
Added freduce -dump
2014-03-06 22:06:58 +01:00
Clifford Wolf
da5859a674
Added freduce -stop
2014-03-06 18:14:26 +01:00
Clifford Wolf
9b9c3327cc
Fixed undef handling in opt_reduce
2014-03-06 14:18:34 +01:00
Clifford Wolf
1ecaf1bb76
Added techmap -max_iter option
2014-03-06 12:15:17 +01:00
Clifford Wolf
96e753041d
fixed freduce for Minisat::SimpSolver: use frozen_literal()
2014-03-03 02:14:27 +01:00
Clifford Wolf
9e99984336
Fixed const folding of $bu0 cells
2014-02-27 04:09:32 +01:00
Clifford Wolf
548519875b
Fixed bug (typo) in passes/opt/opt_const.cc
2014-02-22 17:07:22 +01:00
Clifford Wolf
8b508dc90b
Added workaround for vhdl-style edge triggers from vhdl2verilog to proc_arst
2014-02-21 23:34:45 +01:00
Clifford Wolf
4e43cb7317
Added _TECHMAP_REPLACE_ feature to techmap
2014-02-20 23:42:07 +01:00
Clifford Wolf
737b71c735
Added "extract -ignore_parameters" and "extract -ignore_param ..."
2014-02-20 23:31:13 +01:00
Clifford Wolf
236fc4209c
Added "extract -map %<design_name>"
2014-02-20 23:30:15 +01:00
Clifford Wolf
483c99fe46
Added "design -push" and "design -pop"
2014-02-20 23:28:59 +01:00
Clifford Wolf
0dadfed46d
Added connwrappers command
2014-02-20 20:44:11 +01:00
Clifford Wolf
23a3b488a0
Merge branch 'master' of github.com:cliffordwolf/yosys
2014-02-18 20:05:53 +01:00
Clifford Wolf
a71d09421d
Added techmap support for _TECHMAP_CONNMAP_*_
2014-02-18 19:51:00 +01:00
Clifford Wolf
a78bba1f5c
Added "sat -dump_cnf"
2014-02-18 09:29:08 +01:00
Clifford Wolf
32af10fa9b
Coding style corrections in SatHelper::dump_model_to_vcd()
2014-02-18 09:28:05 +01:00
Clifford Wolf
13051e6acf
Added "sat -initsteps"
2014-02-18 09:03:16 +01:00
Clifford Wolf
0851c2b6ea
Renamed "sat -dump_fail_to_vcd" to "sat -dump_vcd" and some minor cleanups
2014-02-17 13:59:39 +01:00
Andrew Zonenberg
4a948d780a
Added "-dump_fail_to_vcd" argument to SAT solver
2014-02-17 13:52:36 +01:00
Clifford Wolf
ca53ef5098
Better preserve wires when flattening (in comparison to techmap)
2014-02-17 09:44:39 +01:00
Clifford Wolf
6d63f39eb6
Added some additional checks to techmap
2014-02-16 22:18:06 +01:00
Clifford Wolf
a9b11d7c83
Added CONSTMSK and CONSTVAL feature to techmap
2014-02-16 21:58:59 +01:00
Clifford Wolf
28e14ee50a
Fixed handling of "keep" attribute on wires in opt_clean
2014-02-16 21:58:27 +01:00
Clifford Wolf
42ce3db983
Fixed use of selection in splitnets command
2014-02-16 17:39:50 +01:00
Clifford Wolf
d3dc22a90f
Added recursion support to techmap
2014-02-16 17:16:44 +01:00
Clifford Wolf
9a816b65a8
Added != support for relational select pattern
2014-02-16 00:16:54 +01:00
Clifford Wolf
623a68f528
Added iopadmap -bits
2014-02-15 21:59:26 +01:00
Clifford Wolf
cdf0f10760
Fixed dfflibmap for cell libraries with no set-reset-ff
2014-02-15 16:34:12 +01:00
Clifford Wolf
67effc9f5b
Fixed opt_const handling of double invert with non-1 output width
2014-02-15 13:16:08 +01:00
Clifford Wolf
3121d19d95
Added abc -keepff option
2014-02-14 11:28:42 +01:00
Clifford Wolf
de3ea9269a
updated default ABC command strings
2014-02-13 19:14:15 +01:00
Clifford Wolf
a123941618
Updated ABC
2014-02-13 18:56:36 +01:00
Clifford Wolf
cd9e8741a7
Implemented read_verilog -defer
2014-02-13 13:59:13 +01:00
Clifford Wolf
b463907890
Removed double blanks in ABC default command sequences
2014-02-13 08:12:52 +01:00
Clifford Wolf
7664f5d92b
Updated ABC and some related changes
2014-02-13 08:07:08 +01:00
Clifford Wolf
ab71bd0746
Updated ABC to rev e97a6e1d59b9
2014-02-12 08:35:42 +01:00
Clifford Wolf
38469e7686
Various improvements in expose command (added -sep and -cut)
2014-02-09 11:07:46 +01:00
Clifford Wolf
b6f33576d5
Added delete {-input|-output|-port}
2014-02-09 10:03:26 +01:00
Clifford Wolf
b3b5fac191
Bugfix in delete command
2014-02-09 09:34:58 +01:00
Clifford Wolf
85914c36e5
Fixed handling of async reset in expose -evert-dff
2014-02-08 21:26:40 +01:00
Clifford Wolf
db86aaa07d
Build fixes for log cmd
2014-02-08 21:21:51 +01:00
Clifford Wolf
c06de50f05
Merge branch 'master' of github.com:cliffordwolf/yosys
2014-02-08 21:08:46 +01:00
Clifford Wolf
0935e20003
Implemented expose -evert-dff
2014-02-08 21:08:38 +01:00
Johann Glaser
af14bb5f65
added "log" command
2014-02-08 19:19:32 +01:00
Clifford Wolf
7f52c18a22
Fixed bug in collecting of RD_TRANSPARENT parameter in memory_collect
2014-02-08 19:13:19 +01:00
Clifford Wolf
926fa61119
Added various new options to splice command
2014-02-08 16:37:18 +01:00
Clifford Wolf
0c11d04144
Added %a select operator
2014-02-08 16:31:38 +01:00
Clifford Wolf
6644f80d97
Moved some passes to other source directories
2014-02-08 14:39:15 +01:00
Clifford Wolf
03ee63ff80
Added support for "keep" attribute to abc pass
2014-02-08 14:25:29 +01:00
Clifford Wolf
82c98bbbe6
Added opt -purge (frontend to opt_clean -purge)
2014-02-08 14:21:34 +01:00
Clifford Wolf
922d1c9520
Only count non-trivial attributes when findinf master signal in opt_clean
2014-02-08 14:21:04 +01:00
Clifford Wolf
2c51619c2b
Now also move net labes to the right position in splice cmd
2014-02-08 00:06:00 +01:00
Clifford Wolf
274bcef66c
Improved detection of primary wire for a signal in opt_clean
2014-02-07 23:50:17 +01:00
Clifford Wolf
244e8ce1f4
Added splice command
2014-02-07 20:30:56 +01:00
Clifford Wolf
08aa1062b4
Added log_header() to splitnets
2014-02-07 19:51:15 +01:00
Clifford Wolf
fc3b3c4ec3
Added $slice and $concat cell types
2014-02-07 17:44:57 +01:00
Clifford Wolf
99b1e9ee56
Re-enabled abc "retime" after sorting yout the yosys-bigsim problem
2014-02-07 16:36:37 +01:00
Clifford Wolf
366dcd3abf
Fixed use of "cmd_error" in passes/cmds/design.cc
2014-02-07 14:16:42 +01:00
Clifford Wolf
0192f1c66e
Disabled ABC retime for now (elliptic_curve_group testcase in yosys-bigsim failed)
2014-02-06 22:31:58 +01:00
Clifford Wolf
58cb8d65af
Added "retime" to standard ABC recipes
2014-02-06 22:16:20 +01:00
Clifford Wolf
91eab69912
Added copy command
2014-02-06 22:09:21 +01:00
Clifford Wolf
cf593222f2
Added design -stash/-copy-from/-copy-to
2014-02-06 21:52:07 +01:00
Clifford Wolf
37fdb2ca7a
Added support for s: select expressions (wire width)
2014-02-06 19:45:03 +01:00
Clifford Wolf
9428050dd6
Added i:, o:, and x: selection pattern
2014-02-06 19:35:33 +01:00
Clifford Wolf
d7d1c7baf8
Added support for %m selection op
2014-02-06 19:30:08 +01:00
Clifford Wolf
f2fdcef13d
Merge branch 'master' of github.com:cliffordwolf/yosys
2014-02-06 19:22:50 +01:00
Clifford Wolf
fa295a4528
Added generic RTLIL::SigSpec::parse_sel() with support for selection variables
2014-02-06 19:22:46 +01:00
Johann Glaser
34eb77d2bf
new %s: add sub-modules to selection
2014-02-06 17:36:39 +01:00
Clifford Wolf
d4b0f28881
Added support for sat -show @<sel_name>
2014-02-06 17:32:51 +01:00
Clifford Wolf
b1a12c5f37
Added sat -set-init-def and sat -tempinduct-def
2014-02-06 16:15:23 +01:00
Clifford Wolf
594d52e0b6
Added opt_const -undriven
2014-02-06 15:49:03 +01:00
Clifford Wolf
c526e56747
Added expose -dff
2014-02-06 15:48:42 +01:00
Clifford Wolf
c13c5b9b7b
Changed techmap description from "simple" to "generic"
2014-02-06 13:10:06 +01:00
Clifford Wolf
eb8fd4a163
Added miter -make_outcmp
2014-02-06 02:20:55 +01:00
Clifford Wolf
80a1cdb0e2
Added sat -set-init-zero support
2014-02-06 01:40:01 +01:00
Clifford Wolf
e915043144
Added sat -verify and -falsify support for non-prove cases
2014-02-06 00:59:41 +01:00
Clifford Wolf
cd06055e77
Added expose command
2014-02-05 23:59:55 +01:00
Clifford Wolf
dbfcc2f4e2
Simplified select "Assertation failed" message generation
2014-02-05 18:52:55 +01:00
Clifford Wolf
94b802c65d
Merge branch 'master' of github.com:cliffordwolf/yosys
2014-02-05 18:46:47 +01:00
Clifford Wolf
f6e6e9b844
Added selection support for r: and selection with relational operators
2014-02-05 18:24:45 +01:00
Johann Glaser
3c0b5139a1
be more verbose for select -assert-any and -assert-none
2014-02-05 16:03:02 +01:00
Johann Glaser
667543de0b
improved help for "select"
2014-02-05 15:53:02 +01:00
Clifford Wolf
5bf33de24a
Added setattr and setparam commands
2014-02-05 11:11:55 +01:00
Clifford Wolf
1fb8ba73bd
Throw errors if non-existing selection variables are used
2014-02-04 23:31:06 +01:00
Clifford Wolf
b1bf55dd63
Added select -none
2014-02-04 23:23:44 +01:00
Clifford Wolf
99b9c56da1
Fixed detection of init attribute in opt_rmdff
2014-02-04 23:00:32 +01:00
Clifford Wolf
69e867f3e8
Added support for inline commands to abc -script
2014-02-04 22:01:53 +01:00
Clifford Wolf
7a5f378bae
Added hierarchy -purge_lib option
2014-02-04 16:50:13 +01:00
Clifford Wolf
6891fd79a3
added sat -falsify
2014-02-04 13:34:37 +01:00
Clifford Wolf
d267bcde4e
Fixed bug in sequential sat proofs and improved handling of asserts
2014-02-04 12:46:16 +01:00
Clifford Wolf
ecdf1f5577
Improved handling of reg init in opt_share and opt_rmdff
2014-02-04 12:02:47 +01:00
Clifford Wolf
9e35021585
Addred sat option -ignore_unknown_cells
2014-02-03 16:26:10 +01:00
Clifford Wolf
a6750b3753
Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)
2014-02-03 13:01:45 +01:00
Clifford Wolf
de336d93b2
More opt_const -mux_bool features
2014-02-02 22:41:24 +01:00
Clifford Wolf
9d0b69edaa
Added opt_const -mux_bool
2014-02-02 22:11:08 +01:00
Clifford Wolf
bee4450c4c
Added support for inverter chains to opt_const
2014-02-02 21:46:42 +01:00
Clifford Wolf
67b0ce2578
Only generate write-enable $and if WE is not constant 1 in memory_map
2014-02-02 21:27:26 +01:00
Clifford Wolf
83fa652820
Added constant-clock case to opt_rmdff
2014-02-02 21:09:08 +01:00
Clifford Wolf
aa732b0c73
Added show -notitle option
2014-02-02 17:55:32 +01:00
Clifford Wolf
9808acdc75
Added delete command
2014-02-02 17:11:19 +01:00
Clifford Wolf
a9e2d86f86
Added suuport for module attribute matching with A:<pattern>[=<pattern>] syntax
2014-02-02 16:47:17 +01:00
Clifford Wolf
f4f0bd6eef
Fixed a bug in miter command
2014-02-01 22:53:27 +01:00
Clifford Wolf
374674aff4
Added sat -show-inputs and -show-outputs
2014-02-01 22:52:44 +01:00
Clifford Wolf
caf540d1ad
Added show -color support for cells and finished show -label implementation
2014-02-01 18:23:32 +01:00
Clifford Wolf
fa92722358
Added miter command
2014-02-01 10:35:56 +01:00
Johann Glaser
e9a2094774
enabled multiple "-map" for the extract pass
2014-01-25 21:11:34 +01:00
Clifford Wolf
c1ed2607fb
Added support for // comments in liberty parser
2014-01-25 06:32:16 +01:00
Clifford Wolf
32a91458a7
Added hilomap command
2014-01-19 21:58:58 +01:00
Clifford Wolf
03a876c7e8
Added sat -tempinduc and sat -prove-asserts
2014-01-19 16:35:17 +01:00
Clifford Wolf
1e67099b77
Added $assert cell
2014-01-19 14:03:40 +01:00
Clifford Wolf
839af272ad
Improved setundef random number generator
2014-01-18 02:56:36 +01:00
Clifford Wolf
091d9abc3e
Added setundef command
2014-01-17 23:14:36 +01:00
Clifford Wolf
2e370d5a2f
Added support for $adff with undef data inputs to opt_rmdff
2014-01-17 16:42:40 +01:00
Clifford Wolf
651ce67d97
Added select -assert-none and -assert-any
2014-01-17 16:34:50 +01:00
Clifford Wolf
f3154f5694
Added automatic memid generation to memory_unpack command
2014-01-17 00:15:15 +01:00
Clifford Wolf
4d8318ad1b
Added memory_unpack command
2014-01-17 00:05:02 +01:00
Martin Schmölzer
aa17f16fec
Include unistd.h in passes/hierarchy/hierarchy.cc (required for access(3))
...
This fixes compilation errors on Arch Linux.
Signed-off-by: Martin Schmölzer <martin.schmoelzer@student.tuwien.ac.at>
2014-01-14 20:12:45 +01:00
Clifford Wolf
0c5b1f32d4
Added hierarchy -libdir option
2014-01-14 19:28:20 +01:00
Clifford Wolf
9a00980129
renamed LibertyParer to LibertyParser
2014-01-14 18:57:47 +01:00
Clifford Wolf
c1da7661a5
Added "+" to list of liberty token characters
2014-01-14 18:56:29 +01:00
Clifford Wolf
54275c61ee
Added "opt_const -mux_undef"
2014-01-14 11:10:29 +01:00
Clifford Wolf
bc541b47ea
Improved performance of freduce input cone reduction
2014-01-04 13:10:51 +01:00
Clifford Wolf
b791af174e
Improved freduce performance on const signals
2014-01-04 00:06:36 +01:00
Clifford Wolf
10f45b8c8e
Performance improvements in freduce pass
2014-01-03 21:29:28 +01:00
Clifford Wolf
c44e1bec6d
More freduce cleanups
2014-01-03 18:17:28 +01:00
Clifford Wolf
03f0ab9de2
Cleanups in freduce command
2014-01-03 17:50:39 +01:00
Clifford Wolf
8a8d444648
Tiny cleanup in proc_mux.cc
2014-01-03 16:54:59 +01:00
Clifford Wolf
60fbca9970
Added "splitnets -driver"
2014-01-03 14:01:06 +01:00
Clifford Wolf
bf5e5429c1
Use selection in freduce command
2014-01-03 13:15:11 +01:00
Clifford Wolf
c3e9f0712f
Another small freduce cleanup/bugfix
2014-01-03 12:34:18 +01:00
Clifford Wolf
914e208aa3
Added "connect" command
2014-01-03 12:33:00 +01:00
Clifford Wolf
67d155078d
More freduce cleanups and bugfixes
2014-01-03 02:44:05 +01:00
Clifford Wolf
fb2bf934dc
Added correct handling of $memwr priority
2014-01-03 00:22:17 +01:00
Clifford Wolf
536e20bde1
Fixed more complex undef cases in freduce
2014-01-02 23:40:20 +01:00
Clifford Wolf
5a0f561d9c
Now */ is optional in */<mode>:<arg> selections
2014-01-02 20:35:37 +01:00
Clifford Wolf
456ae31a8a
Added "rename -hide" command
2014-01-02 20:23:34 +01:00
Clifford Wolf
0759c97748
More "freduce" related fixes and improvements
2014-01-02 19:37:34 +01:00
Clifford Wolf
ced4d7b321
Added support for module->connections to select %ci, %co and %x handling
2014-01-02 18:44:24 +01:00
Clifford Wolf
c6b33f81eb
Some cleanups in freduce -inv mode (and switched from -noinv to -inv)
2014-01-02 18:11:01 +01:00
Clifford Wolf
249ef8695a
Major rewrite of "freduce" command
2014-01-02 16:52:33 +01:00
Clifford Wolf
e09ebf475c
Fixed use of limited length buffer in ABC blif parser
2013-12-31 21:58:35 +01:00
Clifford Wolf
4892a3ce6d
Added abc -dff and -clk support
2013-12-31 21:25:09 +01:00
Clifford Wolf
be5dab87fd
Now using BLIF as ABC input format
2013-12-31 14:29:29 +01:00
Clifford Wolf
c616802ac7
Always use BLIF as ABC output format
2013-12-31 13:41:16 +01:00
Clifford Wolf
bf607df6d5
Fixed undef extend for bitwise binary ops (bugs in simplemap and satgen)
2013-12-29 17:39:49 +01:00
Clifford Wolf
fe8ec32a1c
Added new cell types to manual
2013-12-28 12:10:32 +01:00
Clifford Wolf
c69c416d28
Added $bu0 cell (for easy correct $eq/$ne mapping)
2013-12-28 12:02:14 +01:00
Clifford Wolf
7f71787599
Added sat -prove-x and -set-def-inputs
2013-12-28 11:24:36 +01:00
Clifford Wolf
bd39263796
Improved $_MUX_ handling in opt_const
2013-12-28 10:30:31 +01:00
Clifford Wolf
d81e3ed3ae
More conservastive $eq/$ne/$eqx/$nex opt_const code
2013-12-28 10:29:22 +01:00
Clifford Wolf
c9699fe76d
More $eq/$ne/$eqx/$nex fixes in opt_const
2013-12-27 15:18:14 +01:00
Clifford Wolf
7b02a44efb
Fixed/improved opt_const $eq/$ne/$eqx/$nex handling
2013-12-27 14:21:24 +01:00
Clifford Wolf
369bf81a70
Added support for non-const === and !== (for miter circuits)
2013-12-27 14:20:15 +01:00
Clifford Wolf
11ffa78677
Added sat -set-def/-set-*-undef support
2013-12-27 13:27:21 +01:00
Clifford Wolf
fb31d10236
Renamed sat -set-undef to -set-any-undef
2013-12-27 13:02:46 +01:00
Clifford Wolf
334b0cc803
Fixed dfflibmap for unused output ports
2013-12-21 20:47:22 +01:00
Clifford Wolf
8856cec308
Now prefer smallest cells in dfflibmap
2013-12-21 08:42:37 +01:00
Clifford Wolf
1fb29050e5
Cleanup of dfflibmap cellmap exploration code
2013-12-20 14:21:18 +01:00
Clifford Wolf
eaf7d9675d
Further improved dfflibmap cellmap exploration
2013-12-20 12:34:34 +01:00
Clifford Wolf
404bcc2d1e
Fixed dfflibmap endless-loop bug
2013-12-20 12:13:51 +01:00
Clifford Wolf
c904f5e197
Prefer non-inverted clocks in dfflibmap
2013-12-19 13:21:57 +01:00
Clifford Wolf
2b90ba1e96
Added sat -max_undef feature
2013-12-07 23:58:55 +01:00
Clifford Wolf
8a815ac741
Added "sat" undef support and "sat -set-init" options
2013-12-07 17:28:51 +01:00
Clifford Wolf
5de57e9970
Fixed compiler warining in passes/sat/eval.cc
2013-12-07 16:19:24 +01:00
Clifford Wolf
325b764341
Added eval -set-undef and eval -table
2013-12-07 11:58:22 +01:00
Clifford Wolf
06d96e8fcf
Fixes in fsm detect/extract for better detection of non-fsm circuits
2013-12-06 12:53:20 +01:00
Clifford Wolf
f4b46ed31e
Replaced signed_parameters API with CONST_FLAG_SIGNED
2013-12-04 14:24:44 +01:00
Clifford Wolf
93a70959f3
Replaced RTLIL::Const::str with generic decoder method
2013-12-04 14:14:05 +01:00
Clifford Wolf
6e227e3666
Fixed submod for non-primitive cells
2013-12-02 12:53:55 +01:00
Clifford Wolf
e881878341
Fixed submod for non-cleaned designs
2013-12-02 12:18:07 +01:00
Clifford Wolf
97efc2ed5f
A fix in memory_dff for write ports with static addresses
2013-12-01 14:08:18 +01:00
Clifford Wolf
7295b25955
Progress on AppNote 011
2013-11-29 16:42:49 +01:00
Clifford Wolf
c60aaf8fa3
Added pattern support to "ls" command
2013-11-28 21:34:41 +01:00
Clifford Wolf
293356e87c
Improved ID matching scheme in select (and thus for all commands)
2013-11-28 21:13:16 +01:00
Clifford Wolf
792bbad448
Fixes and improvements in "show" command
2013-11-28 21:02:19 +01:00
Clifford Wolf
0e52f3fa01
Added "src" attribute to processes
2013-11-28 17:37:50 +01:00
Clifford Wolf
5af7f4db72
Added support for "show -pause" and "show -format dot"
2013-11-28 13:35:28 +01:00
Clifford Wolf
38e7fa6530
Tighter integration of ABC build
2013-11-27 09:08:35 +01:00
Clifford Wolf
bc3cc88719
Started implementing undef support in "sat" command
2013-11-25 21:40:00 +01:00
Clifford Wolf
3d95047ce2
Bugfixes in new "stat" command
2013-11-25 21:08:34 +01:00
Clifford Wolf
4c7d6e63ec
Added "stat" command
2013-11-25 20:43:57 +01:00
Clifford Wolf
61412d167f
Improvements in satgen undef handling
2013-11-25 16:50:45 +01:00
Clifford Wolf
bd65e67d8a
Improvements in satgen undef handling
2013-11-25 15:12:01 +01:00
Clifford Wolf
8c3f4b3957
Started implementing undef handling in satgen
2013-11-25 04:51:33 +01:00
Clifford Wolf
76f7c10cfc
Using simplemap mappers from techmap
2013-11-24 23:31:14 +01:00
Clifford Wolf
3ee33cbdaf
Added simplemap pass
2013-11-24 22:52:30 +01:00
Clifford Wolf
8dafecd34d
Added module->avail_parameters (for advanced techmap features)
2013-11-24 20:29:07 +01:00
Clifford Wolf
4011d47646
Added techmap -D and -I options
2013-11-24 20:04:48 +01:00
Clifford Wolf
20175afd29
Added "techmap -share_map" option
2013-11-24 19:50:25 +01:00
Clifford Wolf
f71e27dbf1
Remove auto_wire framework (smarter than the verilog standard)
2013-11-24 17:29:11 +01:00
Clifford Wolf
609caa23b5
Implemented correct handling of signed module parameters
2013-11-24 17:17:21 +01:00
Clifford Wolf
72b35e0b99
Fixed "flatten" top-module detection: Only use on fully selected designs
2013-11-24 14:10:46 +01:00
Clifford Wolf
28093d9dd2
Added "top" attribute to mark top module in hierarchy
2013-11-24 05:03:43 +01:00
Clifford Wolf
5f9c7fc6ea
Improved handling of techmap special wires
2013-11-23 16:49:58 +01:00
Clifford Wolf
532091afcb
Added more generic _TECHMAP_ wire mechanism to techmap pass
2013-11-23 15:58:06 +01:00
Clifford Wolf
295e352ba6
Renamed "placeholder" to "blackbox"
2013-11-22 15:01:12 +01:00
Clifford Wolf
1c4a6411af
Updated abc
2013-11-21 22:39:10 +01:00
Clifford Wolf
09471846c5
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
Clifford Wolf
84ced2bb8e
Fixed a bug in "add -global_input"
2013-11-21 03:01:20 +01:00
Clifford Wolf
64a5f8f75e
Added "proc_arst -global_arst" feature
2013-11-20 21:00:43 +01:00
Clifford Wolf
2279b2a196
Added "add" command (only wires for now)
2013-11-20 19:37:40 +01:00
Clifford Wolf
63285b300c
Renamed temp module generated by "abc" pass from "logic" to "netlist"
2013-11-19 01:03:57 +01:00
Clifford Wolf
a694324a75
Fixed abc pass blif parser for constant bits
2013-11-13 15:46:28 +01:00
Clifford Wolf
e5b974fa2a
Cleanups and bugfixes in response to new internal cell checker
2013-11-11 00:39:45 +01:00
Clifford Wolf
378cc509cd
Call internal checker more often
2013-11-10 23:24:21 +01:00
Clifford Wolf
223892ac28
Improved user-friendliness of "sat" and "eval" expression parsing
2013-11-09 12:02:27 +01:00
Clifford Wolf
18f9477e95
Added verification of SAT model to "eval -vloghammer_report" command
2013-11-09 11:38:17 +01:00
Clifford Wolf
b04051a0e2
Fixed keep attribute on wires in opt_clean
2013-11-08 05:20:15 +01:00
Clifford Wolf
947bd9b96b
Renamed extend_un0() to extend_u0() and use it in genrtlil
2013-11-07 18:17:10 +01:00
Clifford Wolf
0e1661f84e
Fixed type of sign extension in opt_const $eq/$ne handling
2013-11-07 16:53:28 +01:00
Clifford Wolf
db42a8f89b
Fixed $eq/$ne bitwise optimization in opt_const
2013-11-07 11:54:59 +01:00
Clifford Wolf
f485962c5e
Added handling of unconnected/unspecified signals to eval -vloghammer_report
2013-11-06 22:42:07 +01:00
Clifford Wolf
031a91dc94
Added correct RTL undef handling to eval vloghammer mode
2013-11-06 13:16:47 +01:00
Clifford Wolf
f94266bb42
Added eval -vloghammer_report mode
2013-11-06 04:14:56 +01:00
Clifford Wolf
1d34fd7608
Added support for "keep" attributes on wires
2013-11-05 15:52:29 +01:00
Clifford Wolf
eab536a203
Merge branch 'master' of github.com:cliffordwolf/yosys
2013-11-03 21:13:21 +01:00
Clifford Wolf
f7f0af6f9c
Added resolution of positional arguments to hierarchy pass
2013-11-03 09:42:51 +01:00
Clifford Wolf
0efe16f118
Added placeholder check to dfflibmap and cleaned up some other placeholder checks
2013-10-31 12:27:07 +01:00
Clifford Wolf
b8bfa020fa
Added detection for endless recursion in fsm_detect pass
2013-10-30 00:47:58 +01:00
Clifford Wolf
888c43210b
Fixed help message typo (memory pass)
2013-10-30 00:47:31 +01:00
Clifford Wolf
613750155d
Added -format option to splitnets
2013-10-29 11:01:04 +01:00
Clifford Wolf
ceb971eab9
Added support for i/o buffers to iopadmap
2013-10-26 22:27:40 +02:00
Clifford Wolf
dd56004fc0
Added support for sr flip-flops to dfflibmap
2013-10-24 18:20:06 +02:00
Clifford Wolf
628b994cf6
Added support for complex set-reset flip-flops in proc_dff
2013-10-24 16:54:05 +02:00
Clifford Wolf
e679a5d046
Fixed handling of boolean attributes (passes)
2013-10-24 11:37:54 +02:00
Clifford Wolf
d61699843f
Improved handling of dff with async resets
2013-10-21 14:51:58 +02:00
Clifford Wolf
56ea230676
Added handling of multiple async paths in proc_arst
2013-10-19 00:50:13 +02:00
Clifford Wolf
bfa1a65fa9
Added dffsr support to proc_dff pass
2013-10-18 13:26:52 +02:00
Clifford Wolf
9bc703b964
Improved way of connecting ports in techmap pass
2013-10-17 22:19:38 +02:00
Clifford Wolf
8cc53ef72c
Only prefer connected signals iff they have public names
2013-10-17 22:10:55 +02:00
Clifford Wolf
95dbacefbf
Fixed bug in synthesis of memories that are never written
2013-10-17 21:00:37 +02:00
Clifford Wolf
c20571ca5e
Avoid re-arranging signals on register outputs
2013-10-17 20:48:40 +02:00
Clifford Wolf
f5c0ed6c79
Fixed detection of major wires in opt_clean
2013-10-17 02:41:59 +02:00
Clifford Wolf
96e7abad48
Added iopadmap pass
2013-10-16 16:16:06 +02:00
Clifford Wolf
b6db2d9b33
Moved dfflibmap from passes/dfflibmap to passes/techmap
2013-10-16 15:32:26 +02:00
Clifford Wolf
845590aa8e
Fixed parsing or liberty file statements such as 'clocked_on : "(!CLK)";'
...
Patch by Tim Edwards
2013-10-16 06:32:35 +02:00
Clifford Wolf
288ba9618a
Moved common techlib files to techlibs/common
2013-09-15 11:52:57 +02:00
Clifford Wolf
f8107ab7fc
Some minor documentation fixes
2013-08-21 12:16:44 +02:00
Clifford Wolf
1af1cebb64
Minor fixes in abc build instructions and abc pass
2013-08-20 09:46:05 +02:00
Clifford Wolf
2f3da54f26
Added sat -ignore_div_by_zero switch
2013-08-15 11:40:01 +02:00
Clifford Wolf
d0e93e04d1
Added eval -brute_force_equiv_checker_x mode
2013-08-15 11:09:30 +02:00
Clifford Wolf
a5836af172
Added "clean -purge" and ";;;" support
2013-08-11 13:59:14 +02:00
Clifford Wolf
080f0aac34
Added ";;" as shortcut for "; clean;"
2013-08-11 13:33:38 +02:00
Clifford Wolf
6068b8902f
freduce performance fix
2013-08-10 15:03:13 +02:00
Clifford Wolf
376150c926
Added techmap -opt mode
2013-08-09 15:20:22 +02:00
Clifford Wolf
05483619f0
Some fixes to improve determinism
2013-08-09 12:42:32 +02:00
Clifford Wolf
d97782b848
Sort ctrl signals in fsm_extract
2013-08-08 15:46:00 +02:00
Clifford Wolf
6a40e46a04
Added -try option to freduce pass
2013-08-08 10:56:27 +02:00
Clifford Wolf
8cd153612e
Added "clean" command (less verbose opt_clean)
2013-08-08 10:53:37 +02:00
Clifford Wolf
56e01ce389
Fixed topological ordering in freduce pass
2013-08-07 19:38:19 +02:00
Clifford Wolf
e729857647
Improved handling of private names in opt_clean and rename commands
2013-08-07 18:39:49 +02:00
Clifford Wolf
653750faac
Small bugfixes in freduce pass
2013-08-06 15:53:09 +02:00
Clifford Wolf
6efca9ea5a
Added freduce command
2013-08-06 15:04:52 +02:00
Clifford Wolf
0f38008ed3
Added "design" command (-reset, -save, -load)
2013-07-27 14:27:51 +02:00
Clifford Wolf
88d0829d65
Automatically run "proc" on extract map files
2013-07-24 20:19:08 +02:00
Clifford Wolf
ad9bbcbf40
Added $lut cells and abc lut mapping support
2013-07-23 16:19:34 +02:00
Clifford Wolf
a9fefc6ce1
Bugfixes for empty signal vectors
2013-07-10 12:52:29 +02:00
Clifford Wolf
cf885c4a28
Added opt_clean -purge option
2013-07-07 12:59:30 +02:00
Clifford Wolf
0c0197cf45
Fixed handling of $eq and $ne in opt_const
2013-07-07 12:59:00 +02:00
Clifford Wolf
101491132f
Added SAT support for -all/-max with -verify
2013-06-23 13:28:30 +02:00
Clifford Wolf
46b177eb8a
Merge branch 'master' of github.com:cliffordwolf/yosys
2013-06-20 12:49:28 +02:00
Clifford Wolf
8fbb5b6240
Added timout functionality to SAT solver
2013-06-20 12:49:10 +02:00
Clifford Wolf
a6aeb3dbf0
Added renaming of wires and cells to "rename" command
2013-06-19 16:55:43 +02:00
Clifford Wolf
21e38bed98
Added "eval" pass
2013-06-19 09:30:37 +02:00
Clifford Wolf
48aa72ae8f
Added splitnets command
2013-06-18 17:11:36 +02:00
Clifford Wolf
c09b66b2a1
Added support for "assign" statements in abc vlparse
2013-06-15 13:50:38 +02:00
Clifford Wolf
6d7b5f9064
Fixed even more ConstEval bugs found using xsthammer
2013-06-14 17:50:26 +02:00
Clifford Wolf
30db70b1ba
Added consteval testing to xsthammer and fixed bugs
2013-06-13 19:51:13 +02:00
Clifford Wolf
7f6c83a853
More xsthammer improvements (using xst 14.5 now)
2013-06-13 17:23:51 +02:00
Clifford Wolf
a42dd4549b
Added "scatter" command
2013-06-12 14:41:33 +02:00
Clifford Wolf
49293a182d
Renamed yosys-show temp files to be dot-files in the users home directory
2013-06-12 10:42:59 +02:00
Clifford Wolf
7d790febb0
Improvements and fixes in SAT code
2013-06-10 16:09:29 +02:00
Clifford Wolf
95e937438f
Added "rename" command
2013-06-10 12:37:22 +02:00
Clifford Wolf
08e2fa978c
Renamed "sat_solve" pass to "sat"
2013-06-09 21:55:53 +02:00
Clifford Wolf
a75b249427
Implemented temporal induction proofs in sat_solve
2013-06-09 18:07:05 +02:00
Clifford Wolf
b210234612
Added support for non-temporal proofs to sat_solve
2013-06-09 16:30:37 +02:00
Clifford Wolf
1349b845e3
Re-organization in sat_solver pass for temporal induction
2013-06-09 15:49:32 +02:00
Clifford Wolf
41932e8b64
Added ezSAT api support for don't care values in models
2013-06-09 14:21:18 +02:00
Clifford Wolf
b7ba90910d
Fixed handling of $_XOR_ in SAT generator
2013-06-09 14:01:50 +02:00
Clifford Wolf
0efde13775
Added sequential solving support to sat_solve
2013-06-09 13:35:46 +02:00
Clifford Wolf
bf59a28f80
Look for yosys-abc and yosys-svgviewer where the main exe is
2013-06-09 00:07:26 +02:00
Clifford Wolf
6c8a424872
Added "make abc" and "make install-abc"
2013-06-08 23:48:19 +02:00
Clifford Wolf
5a592b3739
Moved cmds from kernel/ to passes/cmds/
2013-06-08 23:16:36 +02:00
Clifford Wolf
4b7f070b69
Fixed typo is sat_solve help msg
2013-06-08 15:36:32 +02:00
Clifford Wolf
23a7973094
Added support for shifter cells to SAT generator
2013-06-08 15:12:08 +02:00
Clifford Wolf
1434312fdd
Various improvements in sat_solve pass and SAT generator
2013-06-08 14:11:50 +02:00
Clifford Wolf
99957a825f
Added -all and -max options to sat_solve
2013-06-08 12:17:30 +02:00
Clifford Wolf
c681c17038
Improved auto-detection of -show signals in sat_solve
2013-06-08 09:34:36 +02:00
Clifford Wolf
56b593b91c
Improved sat generator and sat_solve pass
2013-06-07 14:37:33 +02:00
Clifford Wolf
46fbe9d262
Added SAT generator and simple sat_solve command
2013-06-07 13:59:13 +02:00
Clifford Wolf
c32b918681
Renamed opt_rmunused to opt_clean
2013-06-05 07:07:31 +02:00
Clifford Wolf
5f2c5f9017
Fixed techmap/flatten for positional module arguments
2013-05-26 12:21:17 +02:00
Clifford Wolf
b11d9408d9
Improved log messages generated by hierarchy pass
2013-05-26 12:20:51 +02:00
Clifford Wolf
cc587fb5f3
Added -nodetect option to fsm pass
2013-05-24 15:34:25 +02:00
Clifford Wolf
66bc46b30b
Improved FSM one-hot encoding, added binary encoding
2013-05-24 14:39:19 +02:00
Clifford Wolf
ccd2a93439
Added log_abort() api
2013-05-24 12:32:06 +02:00
Clifford Wolf
585fcace10
Fixed a gcc vs. clang determinism problem in abc pass
2013-05-23 16:17:23 +02:00
Clifford Wolf
f674150f1c
Fixed memory corruption bug in opt_rmunused
2013-05-23 13:19:28 +02:00
Clifford Wolf
e04d88cf22
Added missing newline to some error messages
2013-05-23 11:19:33 +02:00
Clifford Wolf
3b8882ae49
Some improvements in opt_rmdff
2013-05-23 07:48:18 +02:00
Clifford Wolf
3ecc314238
Fixed to aggressive x-folding in opt_const
2013-05-17 14:55:18 +02:00
Clifford Wolf
83c743f717
Added support for const cell inputs in techmap
2013-04-27 18:30:29 +02:00
Clifford Wolf
b1cb4d7871
Added "flatten" pass
2013-04-26 14:40:45 +02:00
Clifford Wolf
94744ac7b0
Fixed hierarchy pass for hierarchies of parametric modules
2013-04-26 13:28:15 +02:00
Clifford Wolf
6626aad29a
Added "submod -name ..." support
2013-04-15 11:58:24 +02:00
Clifford Wolf
c6198ea5a8
Fixed a bug in opt_const when optimizing 1-bit compares with constants
2013-04-13 21:18:24 +02:00
Johann Glaser
7ef245aa7d
fsm_export: optionally use binary state encoding as state names instead of
...
s0, s1, ...
2013-04-05 15:34:40 +02:00
Johann Glaser
9714072b28
fsm_export: specify KISS filename on command line
2013-04-05 11:17:49 +02:00
Clifford Wolf
88af5b6a16
Improved opt_share for reduce cells
2013-03-29 11:19:21 +01:00
Clifford Wolf
0d48b846ac
Improved opt_share for commutative standard cells
2013-03-29 11:01:26 +01:00
Clifford Wolf
8edf4f378a
Added proper TECHMAP_FAIL support and added support for the celltype attribute in the map file
2013-03-28 10:12:50 +01:00
Clifford Wolf
7bfc7b61a8
Implemented proper handling of stub placeholder modules
2013-03-28 09:20:10 +01:00
Clifford Wolf
9c401b58a2
Added yosys-svgviewer to build system and renamed filterlib to yosys-filterlib
2013-03-27 10:51:15 +01:00
Clifford Wolf
6a231816fa
Collect parameters in hierarchy -generate (and do nothing with them)
2013-03-26 19:11:53 +01:00
Clifford Wolf
227520f94d
Added nosync attribute and some async reset related fixes
2013-03-25 17:13:14 +01:00
Clifford Wolf
0f5378b559
Improved method for finding fsm_expand candidates
2013-03-25 02:24:11 +01:00
Clifford Wolf
4a7d624bef
Added hierarchy -generate command for generating skeletton modules
2013-03-25 02:14:33 +01:00
Clifford Wolf
4bd6f1ee8e
Changed fsm_expand to merge multiplexers more aggressively
2013-03-24 17:59:44 +01:00
Clifford Wolf
8d37d1e08b
Added -nomap option to memory pass
2013-03-21 09:11:06 +01:00
Clifford Wolf
9f10acb840
added optimizations for single-bit $eq/$ne with constant input to opt_const
2013-03-19 13:33:33 +01:00
Clifford Wolf
d8a7fa6b67
improved $mux optimization in opt_const
2013-03-19 13:32:39 +01:00
Clifford Wolf
b7fcf1fb9a
keep $mux and $_MUX_ optimizations separate in opt_const
2013-03-19 13:32:04 +01:00
Johann Glaser
69674652c5
added one more suggestion to optimize MUXes in pass "opt_const"
2013-03-18 22:06:16 +01:00
Johann Glaser
a4e2c887f1
also optimize single-bit "$mux" cells in pass "opt_const", added suggestions
...
for more optimizations
2013-03-18 22:05:21 +01:00
Clifford Wolf
020a35d11e
Removed date from auto-generated passes/techmap/stdcells.inc
2013-03-18 07:32:33 +01:00
Clifford Wolf
52914c2e68
Fixed abc eeror handling
2013-03-18 07:31:59 +01:00
Johann Glaser
3b8ebd694d
add header to autogenerated file on its origin
2013-03-18 07:28:31 +01:00
Johann Glaser
cd8008bda0
fixed typos
2013-03-18 07:28:31 +01:00
Clifford Wolf
ba3793b642
Fixed strerrno vs. strerror types in ABC pass
2013-03-17 09:28:58 +01:00
Clifford Wolf
1390de4b74
Cleaned up ABC file/io error handling
2013-03-17 09:17:18 +01:00
Johann Glaser
0cb4a5936f
added error checking at execution of ABC
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2013-03-17 09:06:03 +01:00
Johann Glaser
fb494d4dd7
corrected typos
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2013-03-17 09:06:02 +01:00
Clifford Wolf
35b4a2c553
Fixed gcc warnings and added error handling to shell escape
2013-03-15 10:29:25 +01:00
Clifford Wolf
cd5767d61b
Added scc pass (find logic loops)
2013-03-15 10:24:08 +01:00
Clifford Wolf
10956cb84a
Added [[CITE]] tags to abc and fsm_extract passes
2013-03-15 10:23:02 +01:00
Clifford Wolf
55f927eecb
Fixed detection of public wires in opt_rmunused
2013-03-10 14:20:03 +01:00
Clifford Wolf
b96ffed69b
Automatically select new objects in abc and techmap passes
2013-03-08 09:16:25 +01:00
Clifford Wolf
ef4f1c55b6
Split extract -attr into extract -cell_attr and -wire_attr
2013-03-08 08:19:24 +01:00
Clifford Wolf
bf3a3b9589
Added support for attribute matching in extract pass
2013-03-07 18:51:17 +01:00
Clifford Wolf
4347423ca6
Changed default value for extract -mine_cells_span
2013-03-05 21:52:57 +01:00
Clifford Wolf
29c17fddf5
Implemented -mine_split option to extract pass
2013-03-05 13:50:31 +01:00
Clifford Wolf
334fd03e1c
Implemented much better #x select operator
2013-03-05 12:53:40 +01:00
Clifford Wolf
efbb89de1a
Implemented extract -mine_max_fanout <num> option
2013-03-03 23:48:00 +01:00
Clifford Wolf
bc8d94b4ae
Added "shared nodes" feature to the subcircuit library
2013-03-03 21:19:55 +01:00
Clifford Wolf
3ebc365c09
Added support for "extract_order" attribute to extract pass
2013-03-03 21:10:27 +01:00
Clifford Wolf
d4680fd5a0
Added design->select() api and use it in extract pass
2013-03-03 20:53:24 +01:00
Clifford Wolf
45bfe26f5f
Minor hotfixes (mostly gcc build fixes)
2013-03-03 13:18:37 +01:00
Clifford Wolf
65e5e1658c
Added library support to celltypes class and show pass
2013-03-03 10:36:23 +01:00
Clifford Wolf
4fcb9a7b99
Implemented general handler for selection arguments
2013-03-03 10:05:37 +01:00
Clifford Wolf
5bed90ae3a
Finished "extract -mine" feature
2013-03-02 18:57:14 +01:00
Clifford Wolf
23eb0ba8bc
Added -mine option to extract pass (not finished)
2013-03-02 16:22:37 +01:00
Clifford Wolf
a338d1a082
Added help messages for fsm_* passes
2013-03-01 12:35:12 +01:00
Clifford Wolf
f3a849512f
Added help messages to memory_* passes
2013-03-01 10:17:35 +01:00
Clifford Wolf
f952309c81
Added help messages to proc_* passes
2013-03-01 09:26:29 +01:00
Clifford Wolf
36954471a6
Added help messages for opt_* passes
2013-03-01 09:01:49 +01:00
Clifford Wolf
7fccad92f7
Added more help messages
2013-03-01 00:36:19 +01:00
Clifford Wolf
af561800ed
Added online help for "show" and "hierarchy" commands
2013-02-28 13:59:49 +01:00
Clifford Wolf
6ac41b2bb1
Added help for command line options
2013-02-28 13:13:56 +01:00
Clifford Wolf
cb592504f4
Added more help messages (extract, abc, dfflibmap)
2013-02-28 11:14:59 +01:00
Clifford Wolf
c3cc9839a9
Added port swapping and compatible types to "extract" pass
2013-02-28 10:00:42 +01:00
Clifford Wolf
08c43f27af
Added "extract -constports" feature
2013-02-27 23:39:10 +01:00
Clifford Wolf
500786af55
Fixed "extract" pass for non-optimized needles
2013-02-27 23:19:30 +01:00
Clifford Wolf
1bbc2b34c8
Added support for simple gates with one constant input to opt_const
2013-02-27 18:00:01 +01:00
Clifford Wolf
da3d55a29c
Added extract -verbose and -map ilang support
2013-02-27 17:26:32 +01:00
Clifford Wolf
f28b6aff40
Implemented basic functionality of "extract" pass
2013-02-27 16:27:20 +01:00
Clifford Wolf
c59d77aa30
Added support for constant signals in "extract" pass
2013-02-27 13:35:30 +01:00
Clifford Wolf
b02e140030
Added "extract" pass (not functional yet)
2013-02-27 13:25:18 +01:00
Clifford Wolf
a321a5c412
Moved stand-alone libs to libs/ directory and added libs/subcircuit
2013-02-27 09:32:19 +01:00
Martin Schmölzer
5a005cefe2
"fsm_export" pass: fix KISS file generation.
...
The KISS file format now follows the conventions specified in
"Logic Synthesis and Optimization Benchmarks User Guide", Version 3.0
by Saeyang Yang.
This change ensures interoperability with the "trfsmgen" program by Johann
Glaser.
Signed-off-by: Martin Schmölzer <martin.schmoelzer@student.tuwien.ac.at>
2013-02-23 18:22:19 +01:00
Martin Schmölzer
4f6cda502d
Add support for "fsm_export" synthesis attributes to fsm_export pass.
...
This allows to specify the file name for exported files directly in the HDL
source via the fsm_export=... attribute on the FSM state register.
Verilog example:
(* fsm_export="my_fsm.kiss2" *)
reg [3:0] state;
The fsm_export pass now also accepts the option "-noauto". This causes only
FSMs with the fsm_export attribute to be exported, any other FSMs are ignored.
Signed-off-by: Martin Schmölzer <martin.schmoelzer@student.tuwien.ac.at>
2013-01-08 09:43:35 +01:00
Clifford Wolf
a7988c01af
Copy attributes from state signal to fsm cell
2013-01-05 11:44:47 +01:00
Clifford Wolf
6543917fb8
added .gitignore files
2013-01-05 11:19:11 +01:00
Clifford Wolf
7764d0ba1d
initial import
2013-01-05 11:13:26 +01:00