mirror of https://github.com/YosysHQ/yosys.git
Cleanup
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416312b9ed
commit
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@ -65,12 +65,9 @@ bool markgroups;
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int map_autoidx;
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SigMap assign_map;
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RTLIL::Module *module;
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std::map<RTLIL::SigBit, int> signal_map;
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std::map<RTLIL::SigBit, RTLIL::State> signal_init;
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bool clk_polarity, en_polarity;
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RTLIL::SigSpec clk_sig, en_sig;
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dict<int, std::string> pi_map, po_map;
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std::string remap_name(RTLIL::IdString abc_name)
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{
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@ -227,13 +224,13 @@ struct abc_output_filter
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void next_line(const std::string &line)
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{
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int pi, po;
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if (sscanf(line.c_str(), "Start-point = pi%d. End-point = po%d.", &pi, &po) == 2) {
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log("ABC: Start-point = pi%d (%s). End-point = po%d (%s).\n",
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pi, pi_map.count(pi) ? pi_map.at(pi).c_str() : "???",
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po, po_map.count(po) ? po_map.at(po).c_str() : "???");
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return;
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}
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//int pi, po;
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//if (sscanf(line.c_str(), "Start-point = pi%d. End-point = po%d.", &pi, &po) == 2) {
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// log("ABC: Start-point = pi%d (%s). End-point = po%d (%s).\n",
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// pi, pi_map.count(pi) ? pi_map.at(pi).c_str() : "???",
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// po, po_map.count(po) ? po_map.at(po).c_str() : "???");
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// return;
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//}
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for (char ch : line)
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next_char(ch);
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@ -249,10 +246,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
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module = current_module;
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map_autoidx = autoidx++;
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signal_map.clear();
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pi_map.clear();
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po_map.clear();
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if (clk_str != "$")
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{
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clk_polarity = true;
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@ -816,10 +809,6 @@ struct Abc9Pass : public Pass {
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log_push();
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assign_map.clear();
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signal_map.clear();
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signal_init.clear();
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pi_map.clear();
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po_map.clear();
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#ifdef ABCEXTERNAL
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std::string exe_file = ABCEXTERNAL;
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@ -970,24 +959,6 @@ struct Abc9Pass : public Pass {
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}
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assign_map.set(mod);
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signal_init.clear();
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for (Wire *wire : mod->wires())
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if (wire->attributes.count("\\init")) {
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SigSpec initsig = assign_map(wire);
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Const initval = wire->attributes.at("\\init");
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for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++)
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switch (initval[i]) {
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case State::S0:
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signal_init[initsig[i]] = State::S0;
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break;
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case State::S1:
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signal_init[initsig[i]] = State::S0;
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break;
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default:
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break;
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}
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}
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if (!retime_mode || !clk_str.empty()) {
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abc9_module(design, mod, script_file, exe_file, cleanup, lut_costs, retime_mode, clk_str, keepff,
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@ -1146,10 +1117,6 @@ struct Abc9Pass : public Pass {
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Pass::call(design, "clean");
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assign_map.clear();
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signal_map.clear();
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signal_init.clear();
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pi_map.clear();
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po_map.clear();
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log_pop();
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}
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