mirror of https://github.com/YosysHQ/yosys.git
Compile abc9
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parent
edf7267019
commit
5a0a5aae4f
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@ -7,6 +7,7 @@ OBJS += passes/techmap/libparse.o
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ifeq ($(ENABLE_ABC),1)
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OBJS += passes/techmap/abc.o
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OBJS += passes/techmap/abc9.o
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ifneq ($(ABCEXTERNAL),)
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passes/techmap/abc.o: CXXFLAGS += -DABCEXTERNAL='"$(ABCEXTERNAL)"'
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endif
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@ -621,7 +621,7 @@ struct abc_output_filter
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}
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};
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void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::string script_file, std::string exe_file,
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void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::string script_file, std::string exe_file,
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std::string liberty_file, std::string constr_file, bool cleanup, vector<int> lut_costs, bool dff_mode, std::string clk_str,
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bool keepff, std::string delay_target, std::string sop_inputs, std::string sop_products, std::string lutin_shared, bool fast_mode,
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const std::vector<RTLIL::Cell*> &cells, bool show_tempdir, bool sop_mode)
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@ -1246,13 +1246,13 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
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log_pop();
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}
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struct AbcPass : public Pass {
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AbcPass() : Pass("abc", "use ABC for technology mapping") { }
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struct Abc9Pass : public Pass {
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Abc9Pass() : Pass("abc9", "use ABC for technology mapping") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" abc [options] [selection]\n");
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log(" abc9 [options] [selection]\n");
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log("\n");
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log("This pass uses the ABC tool [1] for technology mapping of yosys's internal gate\n");
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log("library to a target architecture.\n");
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@ -1422,7 +1422,7 @@ struct AbcPass : public Pass {
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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log_header(design, "Executing ABC pass (technology mapping using ABC).\n");
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log_header(design, "Executing ABC9 pass (technology mapping using ABC).\n");
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log_push();
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assign_map.clear();
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@ -1703,7 +1703,7 @@ struct AbcPass : public Pass {
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}
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if (!dff_mode || !clk_str.empty()) {
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abc_module(design, mod, script_file, exe_file, liberty_file, constr_file, cleanup, lut_costs, dff_mode, clk_str, keepff,
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abc9_module(design, mod, script_file, exe_file, liberty_file, constr_file, cleanup, lut_costs, dff_mode, clk_str, keepff,
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delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, mod->selected_cells(), show_tempdir, sop_mode);
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continue;
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}
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@ -1848,7 +1848,7 @@ struct AbcPass : public Pass {
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clk_sig = assign_map(std::get<1>(it.first));
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en_polarity = std::get<2>(it.first);
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en_sig = assign_map(std::get<3>(it.first));
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abc_module(design, mod, script_file, exe_file, liberty_file, constr_file, cleanup, lut_costs, !clk_sig.empty(), "$",
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abc9_module(design, mod, script_file, exe_file, liberty_file, constr_file, cleanup, lut_costs, !clk_sig.empty(), "$",
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keepff, delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, it.second, show_tempdir, sop_mode);
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assign_map.set(mod);
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}
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@ -1863,6 +1863,6 @@ struct AbcPass : public Pass {
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log_pop();
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}
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} AbcPass;
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} Abc9Pass;
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PRIVATE_NAMESPACE_END
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