mirror of https://github.com/YosysHQ/yosys.git
Added "abc -lut w1:w2"
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@ -587,7 +587,7 @@ struct abc_output_filter
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};
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void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::string script_file, std::string exe_file,
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std::string liberty_file, std::string constr_file, bool cleanup, int lut_mode, bool dff_mode, std::string clk_str,
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std::string liberty_file, std::string constr_file, bool cleanup, int lut_mode, int lut_mode2, bool dff_mode, std::string clk_str,
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bool keepff, std::string delay_target, bool fast_mode, const std::vector<RTLIL::Cell*> &cells, bool show_tempdir)
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{
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module = current_module;
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@ -853,6 +853,8 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
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log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno));
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for (int i = 0; i < lut_mode; i++)
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fprintf(f, "%d 1.00 1.00\n", i+1);
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for (int i = lut_mode; i < lut_mode2; i++)
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fprintf(f, "%d %d.00 1.00\n", i+1, 2 << (i - lut_mode));
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fclose(f);
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}
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@ -1142,6 +1144,12 @@ struct AbcPass : public Pass {
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log(" -lut <width>\n");
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log(" generate netlist using luts of (max) the specified width.\n");
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log("\n");
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log(" -lut <w1>:<w2>\n");
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log(" generate netlist using luts of (max) the specified width <w2>. All\n");
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log(" luts with width <= <w1> have constant cost. for luts larger than <w1>\n");
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log(" the area cost doubles with each additional input bit. the delay cost\n");
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log(" is still constant for all lut widths.\n");
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log("\n");
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log(" -dff\n");
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log(" also pass $_DFF_?_ and $_DFFE_??_ cells through ABC. modules with many\n");
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log(" clock domains are automatically partitioned in clock domains and each\n");
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@ -1186,7 +1194,7 @@ struct AbcPass : public Pass {
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std::string script_file, liberty_file, constr_file, clk_str, delay_target;
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bool fast_mode = false, dff_mode = false, keepff = false, cleanup = true;
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bool show_tempdir = false;
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int lut_mode = 0;
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int lut_mode = 0, lut_mode2 = 0;
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markgroups = false;
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#ifdef _WIN32
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@ -1229,7 +1237,15 @@ struct AbcPass : public Pass {
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continue;
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}
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if (arg == "-lut" && argidx+1 < args.size()) {
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lut_mode = atoi(args[++argidx].c_str());
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string arg = args[++argidx];
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size_t pos = arg.find_first_of(':');
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if (pos != string::npos) {
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lut_mode = atoi(arg.substr(0, pos).c_str());
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lut_mode2 = atoi(arg.substr(pos+1).c_str());
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} else {
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lut_mode = atoi(arg.c_str());
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lut_mode2 = lut_mode;
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}
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continue;
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}
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if (arg == "-fast") {
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@ -1274,7 +1290,7 @@ struct AbcPass : public Pass {
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if (mod->processes.size() > 0)
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log("Skipping module %s as it contains processes.\n", log_id(mod));
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else if (!dff_mode || !clk_str.empty())
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abc_module(design, mod, script_file, exe_file, liberty_file, constr_file, cleanup, lut_mode, dff_mode, clk_str, keepff, delay_target, fast_mode, mod->selected_cells(), show_tempdir);
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abc_module(design, mod, script_file, exe_file, liberty_file, constr_file, cleanup, lut_mode, lut_mode2, dff_mode, clk_str, keepff, delay_target, fast_mode, mod->selected_cells(), show_tempdir);
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else
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{
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assign_map.set(mod);
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@ -1418,7 +1434,7 @@ struct AbcPass : public Pass {
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clk_sig = assign_map(std::get<1>(it.first));
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en_polarity = std::get<2>(it.first);
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en_sig = assign_map(std::get<3>(it.first));
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abc_module(design, mod, script_file, exe_file, liberty_file, constr_file, cleanup, lut_mode,
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abc_module(design, mod, script_file, exe_file, liberty_file, constr_file, cleanup, lut_mode, lut_mode2,
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!clk_sig.empty(), "$", keepff, delay_target, fast_mode, it.second, show_tempdir);
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assign_map.set(mod);
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}
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