mirror of https://github.com/YosysHQ/yosys.git
Add "setundef -anyconst"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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3ab79a231b
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4cd6d5556a
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@ -23,6 +23,13 @@
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#include "kernel/rtlil.h"
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#include "kernel/log.h"
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#define MODE_ZERO 0
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#define MODE_ONE 1
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#define MODE_UNDEF 2
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#define MODE_RANDOM 3
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#define MODE_ANYSEQ 4
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#define MODE_ANYCONST 5
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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@ -34,30 +41,32 @@ struct SetundefWorker
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RTLIL::State next_bit()
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{
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if (next_bit_mode == 0)
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if (next_bit_mode == MODE_ZERO)
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return RTLIL::State::S0;
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if (next_bit_mode == 1)
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if (next_bit_mode == MODE_ONE)
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return RTLIL::State::S1;
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if (next_bit_mode == 2)
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log_abort();
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if (next_bit_mode == 4)
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if (next_bit_mode == MODE_UNDEF)
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return RTLIL::State::Sx;
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// xorshift32
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next_bit_state ^= next_bit_state << 13;
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next_bit_state ^= next_bit_state >> 17;
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next_bit_state ^= next_bit_state << 5;
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log_assert(next_bit_state != 0);
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if (next_bit_mode == MODE_RANDOM)
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{
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// xorshift32
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next_bit_state ^= next_bit_state << 13;
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next_bit_state ^= next_bit_state >> 17;
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next_bit_state ^= next_bit_state << 5;
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log_assert(next_bit_state != 0);
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return ((next_bit_state >> (next_bit_state & 15)) & 16) ? RTLIL::State::S0 : RTLIL::State::S1;
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return ((next_bit_state >> (next_bit_state & 15)) & 16) ? RTLIL::State::S0 : RTLIL::State::S1;
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}
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log_abort();
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}
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void operator()(RTLIL::SigSpec &sig)
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{
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if (next_bit_mode == 2) {
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if (next_bit_mode == MODE_ANYSEQ || next_bit_mode == MODE_ANYCONST) {
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siglist.push_back(&sig);
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return;
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}
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@ -93,6 +102,9 @@ struct SetundefPass : public Pass {
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log(" -anyseq\n");
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log(" replace with $anyseq drivers (for formal)\n");
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log("\n");
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log(" -anyconst\n");
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log(" replace with $anyconst drivers (for formal)\n");
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log("\n");
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log(" -random <seed>\n");
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log(" replace with random bits using the specified integer als seed\n");
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log(" value for the random number generator.\n");
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@ -119,25 +131,31 @@ struct SetundefPass : public Pass {
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}
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if (args[argidx] == "-zero") {
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got_value = true;
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worker.next_bit_mode = 0;
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worker.next_bit_mode = MODE_ZERO;
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worker.next_bit_state = 0;
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continue;
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}
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if (args[argidx] == "-one") {
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got_value = true;
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worker.next_bit_mode = 1;
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worker.next_bit_mode = MODE_ONE;
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worker.next_bit_state = 0;
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continue;
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}
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if (args[argidx] == "-anyseq") {
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got_value = true;
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worker.next_bit_mode = 2;
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worker.next_bit_mode = MODE_ANYSEQ;
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worker.next_bit_state = 0;
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continue;
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}
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if (args[argidx] == "-anyconst") {
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got_value = true;
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worker.next_bit_mode = MODE_ANYCONST;
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worker.next_bit_state = 0;
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continue;
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}
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if (args[argidx] == "-undef") {
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got_value = true;
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worker.next_bit_mode = 4;
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worker.next_bit_mode = MODE_UNDEF;
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worker.next_bit_state = 0;
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continue;
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}
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@ -147,7 +165,7 @@ struct SetundefPass : public Pass {
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}
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if (args[argidx] == "-random" && !got_value && argidx+1 < args.size()) {
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got_value = true;
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worker.next_bit_mode = 3;
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worker.next_bit_mode = MODE_RANDOM;
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worker.next_bit_state = atoi(args[++argidx].c_str()) + 1;
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for (int i = 0; i < 10; i++)
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worker.next_bit();
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@ -274,7 +292,7 @@ struct SetundefPass : public Pass {
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module->rewrite_sigspecs(worker);
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if (worker.next_bit_mode == 2)
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if (worker.next_bit_mode == MODE_ANYSEQ || worker.next_bit_mode == MODE_ANYCONST)
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{
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vector<SigSpec*> siglist;
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siglist.swap(worker.siglist);
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@ -291,7 +309,10 @@ struct SetundefPass : public Pass {
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width++;
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if (width > 0) {
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sig.replace(cursor, module->Anyseq(NEW_ID, width));
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if (worker.next_bit_mode == MODE_ANYSEQ)
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sig.replace(cursor, module->Anyseq(NEW_ID, width));
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else
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sig.replace(cursor, module->Anyconst(NEW_ID, width));
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cursor += width;
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} else {
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cursor++;
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