riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Fix iopadmap for loops between tristate IO buffers 

Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2018-05-15 14:02:27 +02:00
parent edd297fb1c
commit fe80b39f56
1 changed files with 21 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
passes/techmap/iopadmap.cc
View File

@ -175,6 +175,8 @@ struct IopadmapPass : public Pass {
if (!toutpad_celltype.empty() || !tinoutpad_celltype.empty())
{
dict<SigBit, pair<IdString, pool<IdString>>> tbuf_bits;
pool<pair<IdString, IdString>> norewrites;
SigMap rewrites;
for (auto cell : module->cells())
if (cell->type == "$_TBUF_") {
@ -246,6 +248,9 @@ struct IopadmapPass : public Pass {
module->remove(tbuf_cell);
skip_wires[wire->name].insert(i);
norewrites.insert(make_pair(cell->name, RTLIL::escape_id(tinoutpad_portname4)));
rewrites.add(sigmap(wire_bit), owire);
continue;
}
@ -283,6 +288,22 @@ struct IopadmapPass : public Pass {
}
}
}
if (GetSize(norewrites))
{
for (auto cell : module->cells())
for (auto port : cell->connections())
{
if (norewrites.count(make_pair(cell->name, port.first)))
continue;
SigSpec orig_sig = sigmap(port.second);
SigSpec new_sig = rewrites(orig_sig);
if (orig_sig != new_sig)
cell->setPort(port.first, new_sig);
}
}
}
for (auto wire : module->selected_wires())