mirror of https://github.com/YosysHQ/yosys.git
Fixed memory_unpack for initialized memories
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96be31de89
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7462618591
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@ -76,6 +76,23 @@ void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory)
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cell->setPort("\\DATA", memory->getPort("\\WR_DATA").extract(i*mem->width, mem->width));
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}
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Const initval = memory->parameters.at("\\INIT");
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for (int i = 0; i < GetSize(initval) && i/mem->width < (1 << abits); i += mem->width) {
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Const val = initval.extract(i, mem->width, State::Sx);
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for (auto bit : val.bits)
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if (bit != State::Sx)
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goto found_non_undef_initval;
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continue;
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found_non_undef_initval:
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RTLIL::Cell *cell = module->addCell(NEW_ID, "$meminit");
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cell->parameters["\\MEMID"] = mem_name.str();
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cell->parameters["\\ABITS"] = memory->parameters.at("\\ABITS");
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cell->parameters["\\WIDTH"] = memory->parameters.at("\\WIDTH");
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cell->parameters["\\PRIORITY"] = i/mem->width;
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cell->setPort("\\ADDR", SigSpec(i/mem->width, abits));
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cell->setPort("\\DATA", val);
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}
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module->remove(memory);
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}
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