mirror of https://github.com/YosysHQ/yosys.git
Preserve important attributes in splitnets
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@ -54,6 +54,19 @@ struct SplitnetsWorker
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new_wire->port_input = wire->port_input;
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new_wire->port_output = wire->port_output;
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if (wire->attributes.count("\\src"))
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new_wire->attributes["\\src"] = wire->attributes.at("\\src");
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if (wire->attributes.count("\\keep"))
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new_wire->attributes["\\keep"] = wire->attributes.at("\\keep");
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if (wire->attributes.count("\\init")) {
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Const old_init = wire->attributes.at("\\init"), new_init;
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for (int i = offset; i < offset+width; i++)
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new_init.bits.push_back(i < GetSize(old_init) ? old_init.bits.at(i) : State::Sx);
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new_wire->attributes["\\init"] = new_init;
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}
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std::vector<RTLIL::SigBit> sigvec = RTLIL::SigSpec(new_wire).to_sigbit_vector();
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splitmap[wire].insert(splitmap[wire].end(), sigvec.begin(), sigvec.end());
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}
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