mirror of https://github.com/YosysHQ/yosys.git
Add option -expose to setundef pass
Option -expose converts undriven wires to inputs. Example usage: setundef -undriven -expose [selection]
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@ -81,6 +81,9 @@ struct SetundefPass : public Pass {
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log(" -undriven\n");
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log(" also set undriven nets to constant values\n");
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log("\n");
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log(" -expose\n");
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log(" also expose undriven nets as inputs\n");
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log("\n");
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log(" -zero\n");
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log(" replace with bits cleared (0)\n");
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log("\n");
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@ -105,6 +108,7 @@ struct SetundefPass : public Pass {
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{
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bool got_value = false;
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bool undriven_mode = false;
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bool expose_mode = false;
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bool init_mode = false;
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SetundefWorker worker;
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@ -117,6 +121,11 @@ struct SetundefPass : public Pass {
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undriven_mode = true;
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continue;
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}
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if (args[argidx] == "-expose") {
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got_value = true;
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expose_mode = true;
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continue;
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}
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if (args[argidx] == "-zero") {
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got_value = true;
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worker.next_bit_mode = 0;
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@ -157,6 +166,8 @@ struct SetundefPass : public Pass {
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}
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extra_args(args, argidx, design);
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if (expose_mode && !undriven_mode)
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log_cmd_error("Option -expose must be used with option -undriven.\n");
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if (!got_value)
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log_cmd_error("One of the options -zero, -one, -anyseq, or -random <seed> must be specified.\n");
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@ -184,12 +195,21 @@ struct SetundefPass : public Pass {
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undriven_signals.del(sigmap(conn.second));
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RTLIL::SigSpec sig = undriven_signals.export_all();
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for (auto &c : sig.chunks()) {
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RTLIL::SigSpec bits;
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for (int i = 0; i < c.width; i++)
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bits.append(worker.next_bit());
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module->connect(RTLIL::SigSig(c, bits));
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}
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if (expose_mode) {
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for (auto &c : sig.chunks()) {
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c.wire->port_input = true;
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log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(c.wire->name));
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}
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module->fixup_ports();
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}
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else {
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for (auto &c : sig.chunks()) {
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RTLIL::SigSpec bits;
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for (int i = 0; i < c.width; i++)
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bits.append(worker.next_bit());
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module->connect(RTLIL::SigSig(c, bits));
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}
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}
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}
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if (init_mode)
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