mirror of https://github.com/YosysHQ/yosys.git
Moved SatHelper::setup_init() code to SatHelper::setup()
This commit is contained in:
Clifford Wolf
parent
34e833103b
commit
54966679df
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@ -90,109 +90,16 @@ struct SatHelper
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log_cmd_error("Bit %d of %s is undef but option -enable_undef is missing!\n", int(i), log_signal(sig));
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}
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void setup_init(int timestep)
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{
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log ("\nSetting up initial state:\n");
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RTLIL::SigSpec big_lhs, big_rhs;
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for (auto &it : module->wires_)
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{
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if (it.second->attributes.count("\\init") == 0)
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continue;
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RTLIL::SigSpec lhs = sigmap(it.second);
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RTLIL::SigSpec rhs = it.second->attributes.at("\\init");
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log_assert(lhs.size() == rhs.size());
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RTLIL::SigSpec removed_bits;
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for (int i = 0; i < lhs.size(); i++) {
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RTLIL::SigSpec bit = lhs.extract(i, 1);
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if (!satgen.initial_state.check_all(bit)) {
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removed_bits.append(bit);
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lhs.remove(i, 1);
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rhs.remove(i, 1);
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i--;
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}
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}
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if (removed_bits.size())
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log_warning("ignoring initial value on non-register: %s\n", log_signal(removed_bits));
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if (lhs.size()) {
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log("Import set-constraint from init attribute: %s = %s\n", log_signal(lhs), log_signal(rhs));
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big_lhs.remove2(lhs, &big_rhs);
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big_lhs.append(lhs);
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big_rhs.append(rhs);
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}
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}
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for (auto &s : sets_init)
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{
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RTLIL::SigSpec lhs, rhs;
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if (!RTLIL::SigSpec::parse_sel(lhs, design, module, s.first))
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log_cmd_error("Failed to parse lhs set expression `%s'.\n", s.first.c_str());
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if (!RTLIL::SigSpec::parse_rhs(lhs, rhs, module, s.second))
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log_cmd_error("Failed to parse rhs set expression `%s'.\n", s.second.c_str());
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show_signal_pool.add(sigmap(lhs));
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show_signal_pool.add(sigmap(rhs));
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if (lhs.size() != rhs.size())
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log_cmd_error("Set expression with different lhs and rhs sizes: %s (%s, %d bits) vs. %s (%s, %d bits)\n",
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s.first.c_str(), log_signal(lhs), lhs.size(), s.second.c_str(), log_signal(rhs), rhs.size());
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log("Import set-constraint: %s = %s\n", log_signal(lhs), log_signal(rhs));
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big_lhs.remove2(lhs, &big_rhs);
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big_lhs.append(lhs);
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big_rhs.append(rhs);
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}
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if (!satgen.initial_state.check_all(big_lhs)) {
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RTLIL::SigSpec rem = satgen.initial_state.remove(big_lhs);
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log_cmd_error("Found -set-init bits that are not part of the initial_state: %s\n", log_signal(rem));
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}
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if (set_init_def) {
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RTLIL::SigSpec rem = satgen.initial_state.export_all();
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std::vector<int> undef_rem = satgen.importUndefSigSpec(rem, 1);
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ez->assume(ez->NOT(ez->expression(ezSAT::OpOr, undef_rem)));
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}
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if (set_init_undef) {
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RTLIL::SigSpec rem = satgen.initial_state.export_all();
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rem.remove(big_lhs);
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big_lhs.append(rem);
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big_rhs.append(RTLIL::SigSpec(RTLIL::State::Sx, rem.size()));
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}
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if (set_init_zero) {
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RTLIL::SigSpec rem = satgen.initial_state.export_all();
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rem.remove(big_lhs);
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big_lhs.append(rem);
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big_rhs.append(RTLIL::SigSpec(RTLIL::State::S0, rem.size()));
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}
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if (big_lhs.size() == 0) {
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log("No constraints for initial state found.\n\n");
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return;
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}
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log("Final constraint equation: %s = %s\n\n", log_signal(big_lhs), log_signal(big_rhs));
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check_undef_enabled(big_lhs), check_undef_enabled(big_rhs);
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ez->assume(satgen.signals_eq(big_lhs, big_rhs, timestep));
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}
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void setup(int timestep = -1, bool initstate = false)
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{
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if (initstate)
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satgen.setInitState(timestep);
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if (timestep > 0)
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log ("\nSetting up time step %d:\n", timestep);
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else
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log ("\nSetting up SAT problem:\n");
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if (initstate)
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satgen.setInitState(timestep);
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if (timestep > max_timestep)
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max_timestep = timestep;
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@ -346,7 +253,95 @@ struct SatHelper
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}
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if (initstate)
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setup_init(timestep);
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{
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RTLIL::SigSpec big_lhs, big_rhs;
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for (auto &it : module->wires_)
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{
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if (it.second->attributes.count("\\init") == 0)
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continue;
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RTLIL::SigSpec lhs = sigmap(it.second);
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RTLIL::SigSpec rhs = it.second->attributes.at("\\init");
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log_assert(lhs.size() == rhs.size());
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RTLIL::SigSpec removed_bits;
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for (int i = 0; i < lhs.size(); i++) {
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RTLIL::SigSpec bit = lhs.extract(i, 1);
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if (!satgen.initial_state.check_all(bit)) {
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removed_bits.append(bit);
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lhs.remove(i, 1);
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rhs.remove(i, 1);
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i--;
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}
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}
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if (removed_bits.size())
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log_warning("ignoring initial value on non-register: %s\n", log_signal(removed_bits));
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if (lhs.size()) {
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log("Import set-constraint from init attribute: %s = %s\n", log_signal(lhs), log_signal(rhs));
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big_lhs.remove2(lhs, &big_rhs);
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big_lhs.append(lhs);
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big_rhs.append(rhs);
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}
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}
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for (auto &s : sets_init)
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{
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RTLIL::SigSpec lhs, rhs;
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if (!RTLIL::SigSpec::parse_sel(lhs, design, module, s.first))
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log_cmd_error("Failed to parse lhs set expression `%s'.\n", s.first.c_str());
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if (!RTLIL::SigSpec::parse_rhs(lhs, rhs, module, s.second))
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log_cmd_error("Failed to parse rhs set expression `%s'.\n", s.second.c_str());
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show_signal_pool.add(sigmap(lhs));
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show_signal_pool.add(sigmap(rhs));
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if (lhs.size() != rhs.size())
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log_cmd_error("Set expression with different lhs and rhs sizes: %s (%s, %d bits) vs. %s (%s, %d bits)\n",
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s.first.c_str(), log_signal(lhs), lhs.size(), s.second.c_str(), log_signal(rhs), rhs.size());
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log("Import init set-constraint: %s = %s\n", log_signal(lhs), log_signal(rhs));
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big_lhs.remove2(lhs, &big_rhs);
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big_lhs.append(lhs);
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big_rhs.append(rhs);
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}
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if (!satgen.initial_state.check_all(big_lhs)) {
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RTLIL::SigSpec rem = satgen.initial_state.remove(big_lhs);
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log_cmd_error("Found -set-init bits that are not part of the initial_state: %s\n", log_signal(rem));
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}
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if (set_init_def) {
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RTLIL::SigSpec rem = satgen.initial_state.export_all();
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std::vector<int> undef_rem = satgen.importUndefSigSpec(rem, 1);
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ez->assume(ez->NOT(ez->expression(ezSAT::OpOr, undef_rem)));
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}
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if (set_init_undef) {
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RTLIL::SigSpec rem = satgen.initial_state.export_all();
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rem.remove(big_lhs);
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big_lhs.append(rem);
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big_rhs.append(RTLIL::SigSpec(RTLIL::State::Sx, rem.size()));
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}
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if (set_init_zero) {
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RTLIL::SigSpec rem = satgen.initial_state.export_all();
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rem.remove(big_lhs);
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big_lhs.append(rem);
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big_rhs.append(RTLIL::SigSpec(RTLIL::State::S0, rem.size()));
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}
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if (big_lhs.size() == 0) {
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log("No constraints for initial state found.\n\n");
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return;
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}
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log("Final init constraint equation: %s = %s\n", log_signal(big_lhs), log_signal(big_rhs));
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check_undef_enabled(big_lhs), check_undef_enabled(big_rhs);
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ez->assume(satgen.signals_eq(big_lhs, big_rhs, timestep));
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}
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}
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int setup_proof(int timestep = -1)
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