riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Cleanup

This commit is contained in:
Eddie Hung 2019-06-17 15:10:33 -07:00
parent 3ebba74461
commit d80678e581
1 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
passes/techmap/abc9.cc
View File

@ -527,7 +527,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
}
RTLIL::Module* box_module = design->module(cell->type);
if (box_module && box_module->attributes.count("\\abc_box_id"))
boxes.emplace_back(it->second);
boxes.emplace_back(cell);
++it;
}
@ -629,8 +629,8 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
}
}
for (auto cell : boxes)
module->remove(cell);
for (auto cell : boxes)
module->remove(cell);
// Copy connections (and rename) from mapped_mod to module
for (auto conn : mapped_mod->connections()) {