mirror of https://github.com/YosysHQ/yosys.git
Fixed "extract" pass for non-optimized needles
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1bbc2b34c8
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500786af55
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@ -158,18 +158,17 @@ namespace
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RTLIL::Cell *needle_cell = (RTLIL::Cell*)mapping.needleUserData;
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RTLIL::Cell *haystack_cell = (RTLIL::Cell*)mapping.haystackUserData;
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for (auto &conn : needle_cell->connections)
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if (mapping.portMapping.count(conn.first) > 0 && sig2port.has(conn.second))
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{
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RTLIL::SigSpec sig = sigmap(conn.second);
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for (auto &conn : needle_cell->connections) {
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RTLIL::SigSpec sig = sigmap(conn.second);
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if (mapping.portMapping.count(conn.first) > 0 && sig2port.has(sigmap(sig))) {
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sig.expand();
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for (int i = 0; i < sig.width; i++)
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for (auto &port : sig2port.find(sig.chunks[i])) {
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RTLIL::SigSpec bitsig = haystack_cell->connections.at(mapping.portMapping[conn.first]).extract(i, 1);
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cell->connections.at(port.first).replace(port.second, bitsig);
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}
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}
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}
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haystack->cells.erase(haystack_cell->name);
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delete haystack_cell;
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