mirror of https://github.com/YosysHQ/yosys.git
More opt_clean cleanups
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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752553d8e9
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@ -320,22 +320,32 @@ void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
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if (initval.is_fully_undef())
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wire->attributes.erase("\\init");
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bool delete_this_wire = false;
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if (GetSize(wire) == 0) {
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// delete zero-width wires
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goto delete_this_wire;
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} else
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if (wire->port_id != 0 || wire->get_bool_attribute("\\keep") || !initval.is_fully_undef()) {
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/* do not delete anything with "keep" or module ports or initialized wires */
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// do not delete anything with "keep" or module ports or initialized wires
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} else
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if (!purge_mode && check_public_name(wire->name)) {
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/* do not get rid of public names unless in purge mode */
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} else {
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if (!raw_used_signals_noaliases.check_any(s1))
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delete_this_wire = true;
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if (!used_signals_nodrivers.check_any(s2))
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delete_this_wire = true;
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// do not get rid of public names unless in purge mode
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} else
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if (!raw_used_signals_noaliases.check_any(s1)) {
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// delete wires that aren't used by anything directly
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goto delete_this_wire;
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} else
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if (!used_signals_nodrivers.check_any(s2)) {
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// delete wires that aren't used by anything indirectly, even though other wires may alias it
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goto delete_this_wire;
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}
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if (delete_this_wire) {
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if (0)
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{
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delete_this_wire:
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del_wires_queue.insert(wire);
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} else {
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}
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else
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{
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RTLIL::SigSig new_conn;
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for (int i = 0; i < GetSize(s1); i++)
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if (s1[i] != s2[i]) {
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@ -355,25 +365,25 @@ void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
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used_signals.add(new_conn.second);
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module->connect(new_conn);
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}
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}
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if (!used_signals_nodrivers.check_all(s2)) {
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std::string unused_bits;
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for (int i = 0; i < GetSize(s2); i++) {
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if (s2[i].wire == NULL)
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continue;
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if (!used_signals_nodrivers.check(s2[i])) {
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if (!unused_bits.empty())
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unused_bits += " ";
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unused_bits += stringf("%d", i);
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if (!used_signals_nodrivers.check_all(s2)) {
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std::string unused_bits;
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for (int i = 0; i < GetSize(s2); i++) {
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if (s2[i].wire == NULL)
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continue;
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if (!used_signals_nodrivers.check(s2[i])) {
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if (!unused_bits.empty())
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unused_bits += " ";
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unused_bits += stringf("%d", i);
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}
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}
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}
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if (unused_bits.empty() || wire->port_id != 0)
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if (unused_bits.empty() || wire->port_id != 0)
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wire->attributes.erase("\\unused_bits");
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else
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wire->attributes["\\unused_bits"] = RTLIL::Const(unused_bits);
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} else {
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wire->attributes.erase("\\unused_bits");
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else
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wire->attributes["\\unused_bits"] = RTLIL::Const(unused_bits);
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} else {
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wire->attributes.erase("\\unused_bits");
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}
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}
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}
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