mirror of https://github.com/YosysHQ/yosys.git
Added "fsm_expand -full"
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@ -59,6 +59,9 @@ struct FsmPass : public Pass {
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log(" -expand, -norecode, -export, -nomap\n");
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log(" enable or disable passes as indicated above\n");
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log("\n");
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log(" -fullexpand\n");
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log(" call expand with -full option\n");
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log("\n");
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log(" -encoding type\n");
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log(" -fm_set_fsm_file file\n");
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log(" -encfile file\n");
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@ -71,6 +74,7 @@ struct FsmPass : public Pass {
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bool flag_norecode = false;
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bool flag_nodetect = false;
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bool flag_expand = false;
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bool flag_fullexpand = false;
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bool flag_export = false;
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std::string fm_set_fsm_file_opt;
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std::string encfile_opt;
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@ -110,6 +114,10 @@ struct FsmPass : public Pass {
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flag_expand = true;
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continue;
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}
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if (arg == "-fullexpand") {
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flag_fullexpand = true;
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continue;
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}
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if (arg == "-export") {
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flag_export = true;
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continue;
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@ -126,8 +134,8 @@ struct FsmPass : public Pass {
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Pass::call(design, "opt_clean");
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Pass::call(design, "fsm_opt");
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if (flag_expand) {
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Pass::call(design, "fsm_expand");
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if (flag_expand || flag_fullexpand) {
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Pass::call(design, flag_fullexpand ? "fsm_expand -full" : "fsm_expand");
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Pass::call(design, "opt_clean");
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Pass::call(design, "fsm_opt");
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}
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@ -32,6 +32,8 @@ struct FsmExpand
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{
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RTLIL::Module *module;
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RTLIL::Cell *fsm_cell;
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bool full_mode;
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SigMap assign_map;
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SigSet<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> sig2driver, sig2user;
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CellTypes ct;
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@ -45,6 +47,9 @@ struct FsmExpand
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bool is_cell_merge_candidate(RTLIL::Cell *cell)
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{
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if (full_mode || cell->type == "$_MUX_")
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return true;
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if (cell->type == "$mux" || cell->type == "$pmux")
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if (cell->getPort("\\A").size() < 2)
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return true;
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@ -68,17 +73,6 @@ struct FsmExpand
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if (new_signals.size() > 3)
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return false;
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if (cell->hasPort("\\Y")) {
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new_signals.append(assign_map(cell->getPort("\\Y")));
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new_signals.sort_and_unify();
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new_signals.remove_const();
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new_signals.remove(assign_map(fsm_cell->getPort("\\CTRL_IN")));
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new_signals.remove(assign_map(fsm_cell->getPort("\\CTRL_OUT")));
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}
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if (new_signals.size() > 2)
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return false;
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return true;
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}
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@ -200,13 +194,15 @@ struct FsmExpand
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fsm_data.copy_to_cell(fsm_cell);
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}
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FsmExpand(RTLIL::Cell *cell, RTLIL::Design *design, RTLIL::Module *mod)
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FsmExpand(RTLIL::Cell *cell, RTLIL::Design *design, RTLIL::Module *mod, bool full)
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{
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module = mod;
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fsm_cell = cell;
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full_mode = full;
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assign_map.set(module);
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ct.setup_internals();
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ct.setup_stdcells();
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for (auto &cell_it : module->cells_) {
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RTLIL::Cell *c = cell_it.second;
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@ -249,17 +245,31 @@ struct FsmExpandPass : public Pass {
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" fsm_expand [selection]\n");
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log(" fsm_expand [-full] [selection]\n");
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log("\n");
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log("The fsm_extract pass is conservative about the cells that belong to a finite\n");
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log("state machine. This pass can be used to merge additional auxiliary gates into\n");
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log("the finite state machine.\n");
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log("\n");
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log("By default, fsm_expand is still a bit conservative regarding merging larger\n");
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log("word-wide cells. Call with -full to consider all cells for merging.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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bool full_mode = false;
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log_header(design, "Executing FSM_EXPAND pass (merging auxiliary logic into FSMs).\n");
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extra_args(args, 1, design);
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-full") {
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full_mode = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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for (auto &mod_it : design->modules_) {
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if (!design->selected(mod_it.second))
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@ -269,7 +279,7 @@ struct FsmExpandPass : public Pass {
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if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second))
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fsm_cells.push_back(cell_it.second);
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for (auto c : fsm_cells) {
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FsmExpand fsm_expand(c, design, mod_it.second);
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FsmExpand fsm_expand(c, design, mod_it.second, full_mode);
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fsm_expand.execute();
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}
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}
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