mirror of https://github.com/YosysHQ/yosys.git
Some fixes in handling of signed arrays
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parent
81bdf0ad0f
commit
56e2bb88ae
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@ -1271,6 +1271,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
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int mem_width, mem_size, addr_bits;
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is_signed = id2ast->is_signed;
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id2ast->meminfo(mem_width, mem_size, addr_bits);
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RTLIL::SigSpec addr_sig = children[0]->genRTLIL();
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@ -1510,6 +1510,7 @@ skip_dynamic_range_lvalue_expansion:;
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}
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int mem_width, mem_size, addr_bits;
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bool mem_signed = children[0]->id2ast->is_signed;
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children[0]->id2ast->meminfo(mem_width, mem_size, addr_bits);
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int data_range_left = children[0]->id2ast->children[0]->range_left;
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@ -1529,6 +1530,7 @@ skip_dynamic_range_lvalue_expansion:;
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AstNode *wire_data = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(mem_width-1, true), mkconst_int(0, true)));
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wire_data->str = id_data;
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wire_data->is_signed = mem_signed;
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current_ast_mod->children.push_back(wire_data);
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current_scope[wire_data->str] = wire_data;
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while (wire_data->simplify(true, false, false, 1, -1, false, false)) { }
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@ -2894,6 +2896,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod,
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std::string id_addr = sstr.str() + "_ADDR", id_data = sstr.str() + "_DATA";
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int mem_width, mem_size, addr_bits;
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bool mem_signed = children[0]->id2ast->is_signed;
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children[0]->id2ast->meminfo(mem_width, mem_size, addr_bits);
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AstNode *wire_addr = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(addr_bits-1, true), mkconst_int(0, true)));
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@ -2906,6 +2909,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod,
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AstNode *wire_data = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(mem_width-1, true), mkconst_int(0, true)));
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wire_data->str = id_data;
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wire_data->is_reg = true;
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wire_data->is_signed = mem_signed;
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wire_data->attributes["\\nosync"] = AstNode::mkconst_int(1, false);
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mod->children.push_back(wire_data);
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while (wire_data->simplify(true, false, false, 1, -1, false, false)) { }
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@ -2967,6 +2971,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod,
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std::string id_addr = sstr.str() + "_ADDR", id_data = sstr.str() + "_DATA";
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int mem_width, mem_size, addr_bits;
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bool mem_signed = id2ast->is_signed;
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id2ast->meminfo(mem_width, mem_size, addr_bits);
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AstNode *wire_addr = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(addr_bits-1, true), mkconst_int(0, true)));
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@ -2980,6 +2985,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod,
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AstNode *wire_data = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(mem_width-1, true), mkconst_int(0, true)));
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wire_data->str = id_data;
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wire_data->is_reg = true;
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wire_data->is_signed = mem_signed;
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if (block)
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wire_data->attributes["\\nosync"] = AstNode::mkconst_int(1, false);
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mod->children.push_back(wire_data);
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