mirror of https://github.com/YosysHQ/yosys.git
Add basic "mutate -list N" framework
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf
parent
c4575103af
commit
ea8ee24140
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@ -9,4 +9,5 @@ OBJS += passes/sat/assertpmux.o
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OBJS += passes/sat/clk2fflogic.o
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OBJS += passes/sat/async2sync.o
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OBJS += passes/sat/supercover.o
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OBJS += passes/sat/mutate.o
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@ -0,0 +1,229 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct mutate_t {
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std::string mode, src;
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IdString modname, cellname, celltype, cellport;
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SigBit outsigbit;
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int portbit = -1;
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};
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struct mutate_opts_t {
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std::string mode;
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IdString module, cell, port;
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int bit = -1;
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};
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void database_add(std::vector<mutate_t> &database, const mutate_opts_t &opts, const mutate_t &entry)
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{
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if (!opts.module.empty() && opts.module != entry.modname)
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return;
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if (!opts.cell.empty() && opts.cell != entry.cellname)
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return;
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if (!opts.port.empty() && opts.port != entry.cellport)
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return;
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if (opts.bit >= 0 && opts.bit != entry.portbit)
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return;
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database.push_back(entry);
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}
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void database_reduce(std::vector<mutate_t> &database, const mutate_opts_t &opts, int N)
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{
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}
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struct MutatePass : public Pass {
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MutatePass() : Pass("mutate", "generate or apply design mutations") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" mutate -list N [options] [selection]\n");
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log("\n");
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log("Create a list of N mutations using an even sampling.\n");
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log("\n");
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log(" -o filename\n");
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log(" Write list to this file instead of console output\n");
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log("\n");
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log("\n");
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log(" mutate -mode MODE [options]\n");
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log("\n");
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log("Apply the given mutation.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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mutate_opts_t opts;
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string filename;
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int N = -1;
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log_header(design, "Executing MUTATE pass.\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-list" && argidx+1 < args.size()) {
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N = atoi(args[++argidx].c_str());
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continue;
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}
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if (args[argidx] == "-o" && argidx+1 < args.size()) {
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filename = args[++argidx];
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continue;
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}
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if (args[argidx] == "-mode" && argidx+1 < args.size()) {
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opts.mode = args[++argidx];
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continue;
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}
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if (args[argidx] == "-module" && argidx+1 < args.size()) {
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opts.module = RTLIL::escape_id(args[++argidx]);
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continue;
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}
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if (args[argidx] == "-cell" && argidx+1 < args.size()) {
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opts.cell = RTLIL::escape_id(args[++argidx]);
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continue;
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}
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if (args[argidx] == "-port" && argidx+1 < args.size()) {
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opts.port = RTLIL::escape_id(args[++argidx]);
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continue;
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}
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if (args[argidx] == "-bit" && argidx+1 < args.size()) {
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opts.bit = atoi(args[++argidx].c_str());
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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if (N >= 0)
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{
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std::vector<mutate_t> database;
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for (auto module : design->selected_modules())
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{
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if (!opts.module.empty() && module->name != opts.module)
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continue;
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SigMap sigmap(module);
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for (auto wire : module->selected_wires())
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{
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for (SigBit bit : SigSpec(wire))
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{
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SigBit sigbit = sigmap(bit);
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if (bit.wire == nullptr || sigbit.wire == nullptr)
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continue;
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if (!bit.wire->port_id != !sigbit.wire->port_id) {
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if (bit.wire->port_id)
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sigmap.add(bit);
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continue;
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}
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if (!bit.wire->name[0] != !sigbit.wire->name[0]) {
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if (bit.wire->name[0] == '\\')
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sigmap.add(bit);
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continue;
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}
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}
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}
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for (auto cell : module->selected_cells())
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{
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if (!opts.cell.empty() && cell->name != opts.cell)
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continue;
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for (auto &conn : cell->connections())
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{
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for (int i = 0; i < GetSize(conn.second); i++) {
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mutate_t entry;
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entry.mode = "inv";
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entry.src = cell->get_src_attribute();
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entry.modname = module->name;
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entry.cellname = cell->name;
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entry.celltype = cell->type;
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entry.cellport = conn.first;
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entry.portbit = i;
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if (cell->output(conn.first)) {
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SigBit bit = sigmap(conn.second[i]);
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if (bit.wire && bit.wire->name[0] == '\\')
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entry.outsigbit = bit;
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}
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database_add(database, opts, entry);
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}
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}
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}
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}
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log("Raw database size: %d\n", GetSize(database));
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if (N != 0) {
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database_reduce(database, opts, N);
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log("Reduced database size: %d\n", GetSize(database));
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}
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std::ofstream fout;
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if (!filename.empty()) {
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fout.open(filename, std::ios::out | std::ios::trunc);
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if (!fout.is_open())
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log_error("Could not open file \"%s\" with write access.\n", filename.c_str());
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}
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for (auto &entry : database) {
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string str = stringf("mutate -mode %s", entry.mode.c_str());
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if (!entry.modname.empty())
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str += stringf(" -module %s", log_id(entry.modname));
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if (!entry.cellname.empty())
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str += stringf(" -cell %s", log_id(entry.cellname));
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if (!entry.cellport.empty())
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str += stringf(" -port %s", log_id(entry.cellport));
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if (entry.portbit >= 0)
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str += stringf(" -bit %d", entry.portbit);
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if (entry.outsigbit.wire || !entry.src.empty()) {
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str += " #";
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if (!entry.src.empty())
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str += stringf(" %s", entry.src.c_str());
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if (entry.outsigbit.wire)
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str += stringf(" %s", log_signal(entry.outsigbit));
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}
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if (filename.empty())
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log("%s\n", str.c_str());
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else
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fout << str << std::endl;
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}
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return;
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}
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log_cmd_error("Invalid mode: %s\n", opts.mode.c_str());
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}
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} MutatePass;
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PRIVATE_NAMESPACE_END
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