mirror of https://github.com/YosysHQ/yosys.git
recover_reduce: Update documentation
The documentation now describes the commands performed in the deleted recover_reduce script.
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@ -23,25 +23,28 @@
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct RecoverReduceCorePass : public Pass {
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struct RecoverReducePass : public Pass {
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enum GateType {
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And,
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Or,
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Xor
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};
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RecoverReduceCorePass() : Pass("recover_reduce_core", "converts gate chains into $reduce_*") { }
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RecoverReducePass() : Pass("recover_reduce", "converts gate chains into $reduce_* cells") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" recover_reduce_core\n");
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log(" recover_reduce\n");
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log("\n");
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log("converts gate chains into $reduce_*\n");
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log("converts gate chains into $reduce_* cells\n");
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log("\n");
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log("This performs the core step of the recover_reduce command. This step recognizes\n");
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log("chains of gates found by the previous steps and converts these chains into one\n");
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log("logical cell.\n");
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log("This command finds chains of $_AND_, $_OR_, and $_XOR_ cells and replaces them\n");
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log("with their corresponding $reduce_* cells. Because this command only operates on\n");
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log("these cell types, it is recommended to map the design to only these cell types\n");
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log("using the `abc -g` command. Note that, in some cases, it may be more effective\n");
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log("to map the design to only $_AND_ cells, run recover_reduce, map the remaining\n");
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log("parts of the design to AND/OR/XOR cells, and run recover_reduce a second time.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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@ -214,6 +217,6 @@ struct RecoverReduceCorePass : public Pass {
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module->remove(cell);
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}
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}
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} RecoverReduceCorePass;
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} RecoverReducePass;
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PRIVATE_NAMESPACE_END
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