mirror of https://github.com/YosysHQ/yosys.git
recover_reduce: Reindent using tabs
This commit is contained in:
Robert Ou
parent
8a5887464c
commit
74d0f17fd4
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@ -24,196 +24,196 @@ USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct RecoverReduceCorePass : public Pass {
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enum GateType {
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And,
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Or,
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Xor
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};
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enum GateType {
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And,
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Or,
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Xor
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};
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RecoverReduceCorePass() : Pass("recover_reduce_core", "converts gate chains into $reduce_*") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" recover_reduce_core\n");
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log("\n");
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log("converts gate chains into $reduce_*\n");
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log("\n");
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log("This performs the core step of the recover_reduce command. This step recognizes\n");
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log("chains of gates found by the previous steps and converts these chains into one\n");
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log("logical cell.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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(void)args;
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RecoverReduceCorePass() : Pass("recover_reduce_core", "converts gate chains into $reduce_*") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" recover_reduce_core\n");
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log("\n");
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log("converts gate chains into $reduce_*\n");
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log("\n");
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log("This performs the core step of the recover_reduce command. This step recognizes\n");
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log("chains of gates found by the previous steps and converts these chains into one\n");
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log("logical cell.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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(void)args;
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for (auto module : design->selected_modules())
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{
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SigMap sigmap(module);
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for (auto module : design->selected_modules())
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{
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SigMap sigmap(module);
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// Index all of the nets in the module
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dict<SigBit, Cell*> sig_to_driver;
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dict<SigBit, pool<Cell*>> sig_to_sink;
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for (auto cell : module->selected_cells())
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{
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for (auto &conn : cell->connections())
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{
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if (cell->output(conn.first))
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for (auto bit : sigmap(conn.second))
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sig_to_driver[bit] = cell;
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// Index all of the nets in the module
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dict<SigBit, Cell*> sig_to_driver;
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dict<SigBit, pool<Cell*>> sig_to_sink;
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for (auto cell : module->selected_cells())
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{
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for (auto &conn : cell->connections())
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{
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if (cell->output(conn.first))
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for (auto bit : sigmap(conn.second))
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sig_to_driver[bit] = cell;
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if (cell->input(conn.first))
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{
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for (auto bit : sigmap(conn.second))
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{
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if (sig_to_sink.count(bit) == 0)
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sig_to_sink[bit] = pool<Cell*>();
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sig_to_sink[bit].insert(cell);
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}
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}
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}
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}
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if (cell->input(conn.first))
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{
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for (auto bit : sigmap(conn.second))
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{
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if (sig_to_sink.count(bit) == 0)
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sig_to_sink[bit] = pool<Cell*>();
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sig_to_sink[bit].insert(cell);
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}
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}
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}
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}
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// Need to check if any wires connect to module ports
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pool<SigBit> port_sigs;
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for (auto wire : module->selected_wires())
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if (wire->port_input || wire->port_output)
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for (auto bit : sigmap(wire))
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port_sigs.insert(bit);
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// Need to check if any wires connect to module ports
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pool<SigBit> port_sigs;
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for (auto wire : module->selected_wires())
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if (wire->port_input || wire->port_output)
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for (auto bit : sigmap(wire))
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port_sigs.insert(bit);
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// Actual logic starts here
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pool<Cell*> consumed_cells;
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for (auto cell : module->selected_cells())
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{
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if (consumed_cells.count(cell))
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continue;
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// Actual logic starts here
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pool<Cell*> consumed_cells;
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for (auto cell : module->selected_cells())
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{
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if (consumed_cells.count(cell))
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continue;
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GateType gt;
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GateType gt;
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if (cell->type == "$_AND_")
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gt = GateType::And;
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else if (cell->type == "$_OR_")
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gt = GateType::Or;
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else if (cell->type == "$_XOR_")
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gt = GateType::Xor;
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else
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continue;
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if (cell->type == "$_AND_")
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gt = GateType::And;
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else if (cell->type == "$_OR_")
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gt = GateType::Or;
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else if (cell->type == "$_XOR_")
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gt = GateType::Xor;
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else
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continue;
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log("Working on cell %s...\n", cell->name.c_str());
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log("Working on cell %s...\n", cell->name.c_str());
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// Go all the way to the sink
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Cell* head_cell = cell;
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Cell* x = cell;
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while (true)
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{
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if (!((x->type == "$_AND_" && gt == GateType::And) ||
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(x->type == "$_OR_" && gt == GateType::Or) ||
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(x->type == "$_XOR_" && gt == GateType::Xor)))
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break;
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// Go all the way to the sink
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Cell* head_cell = cell;
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Cell* x = cell;
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while (true)
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{
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if (!((x->type == "$_AND_" && gt == GateType::And) ||
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(x->type == "$_OR_" && gt == GateType::Or) ||
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(x->type == "$_XOR_" && gt == GateType::Xor)))
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break;
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head_cell = x;
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head_cell = x;
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auto y = sigmap(x->getPort("\\Y"));
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log_assert(y.size() == 1);
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auto y = sigmap(x->getPort("\\Y"));
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log_assert(y.size() == 1);
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// Should only continue if there is one fanout back into a cell (not to a port)
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if (sig_to_sink[y[0]].size() != 1)
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break;
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// Should only continue if there is one fanout back into a cell (not to a port)
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if (sig_to_sink[y[0]].size() != 1)
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break;
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x = *sig_to_sink[y[0]].begin();
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}
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x = *sig_to_sink[y[0]].begin();
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}
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log(" Head cell is %s\n", head_cell->name.c_str());
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log(" Head cell is %s\n", head_cell->name.c_str());
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pool<Cell*> cur_supercell;
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std::deque<Cell*> bfs_queue = {head_cell};
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while (bfs_queue.size())
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{
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Cell* x = bfs_queue.front();
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bfs_queue.pop_front();
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pool<Cell*> cur_supercell;
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std::deque<Cell*> bfs_queue = {head_cell};
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while (bfs_queue.size())
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{
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Cell* x = bfs_queue.front();
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bfs_queue.pop_front();
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cur_supercell.insert(x);
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cur_supercell.insert(x);
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auto a = sigmap(x->getPort("\\A"));
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log_assert(a.size() == 1);
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// Must have only one sink
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// XXX: Check that it is indeed this node?
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if (sig_to_sink[a[0]].size() + port_sigs.count(a[0]) == 1)
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{
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Cell* cell_a = sig_to_driver[a[0]];
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if (((cell_a->type == "$_AND_" && gt == GateType::And) ||
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(cell_a->type == "$_OR_" && gt == GateType::Or) ||
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(cell_a->type == "$_XOR_" && gt == GateType::Xor)))
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{
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// The cell here is the correct type, and it's definitely driving only
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// this current cell.
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bfs_queue.push_back(cell_a);
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}
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}
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auto a = sigmap(x->getPort("\\A"));
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log_assert(a.size() == 1);
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// Must have only one sink
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// XXX: Check that it is indeed this node?
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if (sig_to_sink[a[0]].size() + port_sigs.count(a[0]) == 1)
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{
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Cell* cell_a = sig_to_driver[a[0]];
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if (((cell_a->type == "$_AND_" && gt == GateType::And) ||
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(cell_a->type == "$_OR_" && gt == GateType::Or) ||
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(cell_a->type == "$_XOR_" && gt == GateType::Xor)))
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{
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// The cell here is the correct type, and it's definitely driving only
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// this current cell.
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bfs_queue.push_back(cell_a);
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}
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}
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auto b = sigmap(x->getPort("\\B"));
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log_assert(b.size() == 1);
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// Must have only one sink
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// XXX: Check that it is indeed this node?
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if (sig_to_sink[b[0]].size() + port_sigs.count(b[0]) == 1)
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{
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Cell* cell_b = sig_to_driver[b[0]];
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if (((cell_b->type == "$_AND_" && gt == GateType::And) ||
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(cell_b->type == "$_OR_" && gt == GateType::Or) ||
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(cell_b->type == "$_XOR_" && gt == GateType::Xor)))
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{
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// The cell here is the correct type, and it's definitely driving only
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// this current cell.
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bfs_queue.push_back(cell_b);
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}
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}
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}
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auto b = sigmap(x->getPort("\\B"));
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log_assert(b.size() == 1);
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// Must have only one sink
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// XXX: Check that it is indeed this node?
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if (sig_to_sink[b[0]].size() + port_sigs.count(b[0]) == 1)
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{
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Cell* cell_b = sig_to_driver[b[0]];
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if (((cell_b->type == "$_AND_" && gt == GateType::And) ||
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(cell_b->type == "$_OR_" && gt == GateType::Or) ||
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(cell_b->type == "$_XOR_" && gt == GateType::Xor)))
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{
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// The cell here is the correct type, and it's definitely driving only
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// this current cell.
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bfs_queue.push_back(cell_b);
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}
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}
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}
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log(" Cells:\n");
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for (auto x : cur_supercell)
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log(" %s\n", x->name.c_str());
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log(" Cells:\n");
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for (auto x : cur_supercell)
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log(" %s\n", x->name.c_str());
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if (cur_supercell.size() > 1)
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{
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// Worth it to create reduce cell
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log(" Creating $reduce_* cell!\n");
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if (cur_supercell.size() > 1)
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{
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// Worth it to create reduce cell
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log(" Creating $reduce_* cell!\n");
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pool<SigBit> input_pool;
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pool<SigBit> input_pool_intermed;
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for (auto x : cur_supercell)
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{
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input_pool.insert(sigmap(x->getPort("\\A"))[0]);
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input_pool.insert(sigmap(x->getPort("\\B"))[0]);
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input_pool_intermed.insert(sigmap(x->getPort("\\Y"))[0]);
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}
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SigSpec input;
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for (auto b : input_pool)
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if (input_pool_intermed.count(b) == 0)
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input.append_bit(b);
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pool<SigBit> input_pool;
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pool<SigBit> input_pool_intermed;
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for (auto x : cur_supercell)
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{
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input_pool.insert(sigmap(x->getPort("\\A"))[0]);
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input_pool.insert(sigmap(x->getPort("\\B"))[0]);
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input_pool_intermed.insert(sigmap(x->getPort("\\Y"))[0]);
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}
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SigSpec input;
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for (auto b : input_pool)
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if (input_pool_intermed.count(b) == 0)
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input.append_bit(b);
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SigBit output = sigmap(head_cell->getPort("\\Y")[0]);
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SigBit output = sigmap(head_cell->getPort("\\Y")[0]);
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auto new_reduce_cell = module->addCell(NEW_ID,
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gt == GateType::And ? "$reduce_and" :
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gt == GateType::Or ? "$reduce_or" :
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gt == GateType::Xor ? "$reduce_xor" : "");
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new_reduce_cell->setParam("\\A_SIGNED", 0);
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new_reduce_cell->setParam("\\A_WIDTH", input.size());
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new_reduce_cell->setParam("\\Y_WIDTH", 1);
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new_reduce_cell->setPort("\\A", input);
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new_reduce_cell->setPort("\\Y", output);
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auto new_reduce_cell = module->addCell(NEW_ID,
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gt == GateType::And ? "$reduce_and" :
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gt == GateType::Or ? "$reduce_or" :
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gt == GateType::Xor ? "$reduce_xor" : "");
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new_reduce_cell->setParam("\\A_SIGNED", 0);
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new_reduce_cell->setParam("\\A_WIDTH", input.size());
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new_reduce_cell->setParam("\\Y_WIDTH", 1);
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new_reduce_cell->setPort("\\A", input);
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new_reduce_cell->setPort("\\Y", output);
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for (auto x : cur_supercell)
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consumed_cells.insert(x);
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}
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}
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for (auto x : cur_supercell)
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consumed_cells.insert(x);
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}
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}
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// Remove every cell that we've used up
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for (auto cell : consumed_cells)
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module->remove(cell);
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}
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}
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// Remove every cell that we've used up
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for (auto cell : consumed_cells)
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module->remove(cell);
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}
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}
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} RecoverReduceCorePass;
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PRIVATE_NAMESPACE_END
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