mirror of https://github.com/YosysHQ/yosys.git
Added miter command
This commit is contained in:
Clifford Wolf
parent
1c8f6f21b4
commit
fa92722358
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@ -2,4 +2,5 @@
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OBJS += passes/sat/sat.o
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OBJS += passes/sat/freduce.o
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OBJS += passes/sat/eval.o
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OBJS += passes/sat/miter.o
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@ -0,0 +1,306 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/rtlil.h"
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#include "kernel/log.h"
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static void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL::Design *design)
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{
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bool flag_ignore_gold_x = false;
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bool flag_make_outputs = false;
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bool flag_make_assert = false;
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size_t argidx;
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for (argidx = 2; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-ignore_gold_x") {
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flag_ignore_gold_x = true;
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continue;
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}
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if (args[argidx] == "-make_outputs") {
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flag_make_outputs = true;
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continue;
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}
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if (args[argidx] == "-make_assert") {
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flag_make_assert = true;
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continue;
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}
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break;
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}
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if (argidx+3 != args.size() || args[argidx].substr(0, 1) == "-")
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that->cmd_error(args, argidx, "command argument error");
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std::string gold_name = RTLIL::escape_id(args[argidx++]);
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std::string gate_name = RTLIL::escape_id(args[argidx++]);
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std::string miter_name = RTLIL::escape_id(args[argidx++]);
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if (design->modules.count(gold_name) == 0)
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log_cmd_error("Can't find gold module %s!\n", gold_name.c_str());
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if (design->modules.count(gate_name) == 0)
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log_cmd_error("Can't find gate module %s!\n", gate_name.c_str());
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if (design->modules.count(miter_name) != 0)
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log_cmd_error("There is already a module %s!\n", gate_name.c_str());
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RTLIL::Module *gold_module = design->modules.at(gold_name);
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RTLIL::Module *gate_module = design->modules.at(gate_name);
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for (auto &it : gold_module->wires) {
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RTLIL::Wire *w1 = it.second, *w2;
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if (w1->port_id == 0)
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continue;
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if (gate_module->wires.count(it.second->name) == 0)
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goto match_gold_port_error;
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w2 = gate_module->wires.at(it.second->name);
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if (w1->port_input != w2->port_input)
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goto match_gold_port_error;
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if (w1->port_output != w2->port_output)
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goto match_gold_port_error;
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if (w1->width != w2->width)
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goto match_gold_port_error;
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continue;
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match_gold_port_error:
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log_cmd_error("No matching port in gate module was found for %s!\n", it.second->name.c_str());
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}
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for (auto &it : gate_module->wires) {
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RTLIL::Wire *w1 = it.second, *w2;
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if (w1->port_id == 0)
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continue;
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if (gold_module->wires.count(it.second->name) == 0)
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goto match_gate_port_error;
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w2 = gold_module->wires.at(it.second->name);
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if (w1->port_input != w2->port_input)
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goto match_gate_port_error;
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if (w1->port_output != w2->port_output)
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goto match_gate_port_error;
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if (w1->width != w2->width)
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goto match_gate_port_error;
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continue;
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match_gate_port_error:
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log_cmd_error("No matching port in gold module was found for %s!\n", it.second->name.c_str());
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}
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RTLIL::Module *miter_module = new RTLIL::Module;
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miter_module->name = miter_name;
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design->modules[miter_name] = miter_module;
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RTLIL::Cell *gold_cell = new RTLIL::Cell;
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gold_cell->name = "\\gold";
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gold_cell->type = gold_name;
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miter_module->add(gold_cell);
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RTLIL::Cell *gate_cell = new RTLIL::Cell;
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gate_cell->name = "\\gate";
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gate_cell->type = gate_name;
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miter_module->add(gate_cell);
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RTLIL::SigSpec all_conditions;
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for (auto &it : gold_module->wires)
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{
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RTLIL::Wire *w1 = it.second;
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if (w1->port_input)
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{
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RTLIL::Wire *w2 = new RTLIL::Wire;
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w2->name = "\\in_" + RTLIL::unescape_id(w1->name);
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w2->port_input = true;
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w2->width = w1->width;
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miter_module->add(w2);
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gold_cell->connections[w1->name] = w2;
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gate_cell->connections[w1->name] = w2;
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}
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if (w1->port_output)
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{
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RTLIL::Wire *w2_gold = new RTLIL::Wire;
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w2_gold->name = "\\gold_" + RTLIL::unescape_id(w1->name);
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w2_gold->port_output = flag_make_outputs;
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w2_gold->width = w1->width;
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miter_module->add(w2_gold);
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RTLIL::Wire *w2_gate = new RTLIL::Wire;
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w2_gate->name = "\\gate_" + RTLIL::unescape_id(w1->name);
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w2_gate->port_output = flag_make_outputs;
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w2_gate->width = w1->width;
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miter_module->add(w2_gate);
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gold_cell->connections[w1->name] = w2_gold;
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gate_cell->connections[w1->name] = w2_gate;
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if (flag_ignore_gold_x)
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{
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RTLIL::SigSpec gold_x = miter_module->new_wire(w2_gold->width, NEW_ID);
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for (int i = 0; i < w2_gold->width; i++) {
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RTLIL::Cell *eqx_cell = new RTLIL::Cell;
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eqx_cell->name = NEW_ID;
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eqx_cell->type = "$eqx";
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eqx_cell->parameters["\\A_WIDTH"] = 1;
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eqx_cell->parameters["\\B_WIDTH"] = 1;
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eqx_cell->parameters["\\Y_WIDTH"] = 1;
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eqx_cell->parameters["\\A_SIGNED"] = 0;
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eqx_cell->parameters["\\B_SIGNED"] = 0;
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eqx_cell->connections["\\A"] = RTLIL::SigSpec(w2_gold, 1, i);
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eqx_cell->connections["\\B"] = RTLIL::State::Sx;
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eqx_cell->connections["\\Y"] = gold_x.extract(i, 1);
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miter_module->add(eqx_cell);
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}
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RTLIL::SigSpec gold_masked = miter_module->new_wire(w2_gold->width, NEW_ID);
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RTLIL::SigSpec gate_masked = miter_module->new_wire(w2_gate->width, NEW_ID);
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RTLIL::Cell *or_gold_cell = new RTLIL::Cell;
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or_gold_cell->name = NEW_ID;
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or_gold_cell->type = "$or";
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or_gold_cell->parameters["\\A_WIDTH"] = w2_gold->width;
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or_gold_cell->parameters["\\B_WIDTH"] = w2_gold->width;
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or_gold_cell->parameters["\\Y_WIDTH"] = w2_gold->width;
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or_gold_cell->parameters["\\A_SIGNED"] = 0;
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or_gold_cell->parameters["\\B_SIGNED"] = 0;
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or_gold_cell->connections["\\A"] = w2_gold;
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or_gold_cell->connections["\\B"] = gold_x;
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or_gold_cell->connections["\\Y"] = gold_masked;
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miter_module->add(or_gold_cell);
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RTLIL::Cell *or_gate_cell = new RTLIL::Cell;
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or_gate_cell->name = NEW_ID;
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or_gate_cell->type = "$or";
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or_gate_cell->parameters["\\A_WIDTH"] = w2_gate->width;
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or_gate_cell->parameters["\\B_WIDTH"] = w2_gate->width;
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or_gate_cell->parameters["\\Y_WIDTH"] = w2_gate->width;
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or_gate_cell->parameters["\\A_SIGNED"] = 0;
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or_gate_cell->parameters["\\B_SIGNED"] = 0;
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or_gate_cell->connections["\\A"] = w2_gate;
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or_gate_cell->connections["\\B"] = gold_x;
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or_gate_cell->connections["\\Y"] = gate_masked;
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miter_module->add(or_gate_cell);
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RTLIL::Cell *eq_cell = new RTLIL::Cell;
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eq_cell->name = NEW_ID;
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eq_cell->type = "$eq";
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eq_cell->parameters["\\A_WIDTH"] = w2_gold->width;
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eq_cell->parameters["\\B_WIDTH"] = w2_gate->width;
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eq_cell->parameters["\\Y_WIDTH"] = 1;
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eq_cell->parameters["\\A_SIGNED"] = 0;
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eq_cell->parameters["\\B_SIGNED"] = 0;
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eq_cell->connections["\\A"] = gold_masked;
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eq_cell->connections["\\B"] = gate_masked;
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eq_cell->connections["\\Y"] = miter_module->new_wire(1, NEW_ID);
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all_conditions.append(eq_cell->connections["\\Y"]);
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miter_module->add(eq_cell);
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}
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else
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{
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RTLIL::Cell *eq_cell = new RTLIL::Cell;
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eq_cell->name = NEW_ID;
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eq_cell->type = "$eq";
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eq_cell->parameters["\\A_WIDTH"] = w2_gold->width;
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eq_cell->parameters["\\B_WIDTH"] = w2_gate->width;
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eq_cell->parameters["\\Y_WIDTH"] = 1;
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eq_cell->parameters["\\A_SIGNED"] = 0;
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eq_cell->parameters["\\B_SIGNED"] = 0;
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eq_cell->connections["\\A"] = w2_gold;
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eq_cell->connections["\\B"] = w2_gate;
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eq_cell->connections["\\Y"] = miter_module->new_wire(1, NEW_ID);
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all_conditions.append(eq_cell->connections["\\Y"]);
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miter_module->add(eq_cell);
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}
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}
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}
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if (all_conditions.width != 1) {
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RTLIL::Cell *reduce_cell = new RTLIL::Cell;
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reduce_cell->name = NEW_ID;
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reduce_cell->type = "$reduce_and";
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reduce_cell->parameters["\\A_WIDTH"] = all_conditions.width;
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reduce_cell->parameters["\\Y_WIDTH"] = 1;
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reduce_cell->parameters["\\A_SIGNED"] = 0;
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reduce_cell->connections["\\A"] = all_conditions;
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reduce_cell->connections["\\Y"] = miter_module->new_wire(1, NEW_ID);
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all_conditions = reduce_cell->connections["\\Y"];
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miter_module->add(reduce_cell);
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}
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if (flag_make_assert) {
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RTLIL::Cell *assert_cell = new RTLIL::Cell;
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assert_cell->name = NEW_ID;
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assert_cell->type = "$assert";
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assert_cell->connections["\\A"] = all_conditions;
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assert_cell->connections["\\EN"] = RTLIL::SigSpec(1, 1);
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miter_module->add(assert_cell);
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}
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RTLIL::Wire *w_trigger = new RTLIL::Wire;
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w_trigger->name = "\\trigger";
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w_trigger->port_output = true;
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miter_module->add(w_trigger);
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RTLIL::Cell *not_cell = new RTLIL::Cell;
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not_cell->name = NEW_ID;
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not_cell->type = "$not";
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not_cell->parameters["\\A_WIDTH"] = all_conditions.width;
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not_cell->parameters["\\A_WIDTH"] = all_conditions.width;
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not_cell->parameters["\\Y_WIDTH"] = w_trigger->width;
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not_cell->parameters["\\A_SIGNED"] = 0;
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not_cell->connections["\\A"] = all_conditions;
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not_cell->connections["\\Y"] = w_trigger;
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miter_module->add(not_cell);
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miter_module->fixup_ports();
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}
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struct MiterPass : public Pass {
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MiterPass() : Pass("miter", "automatically create a miter circuit") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" miter -equiv [options] gold_name gate_name miter_name\n");
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log("\n");
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log("Creates a miter circuit for equivialence checking. The gold- and gate- modules\n");
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log("must have the same interfaces. The miter circuit will have all inputs of the\n");
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log("two source modules, prefixed with 'in_'. The miter circuit has a 'trigger'\n");
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log("output that goes high if an output mismatch between the two source modules is\n");
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log("detected.\n");
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log("\n");
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log(" -ignore_gold_x\n");
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log(" a undef (x) bit in the gold module output will match any value in\n");
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log(" the gate module output.\n");
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log("\n");
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log(" -make_outputs\n");
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log(" also route the gold- and gate-outputs to 'gold_*' and 'gate_*' outputs\n");
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log(" on the miter circuit.\n");
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log("\n");
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log(" -make_assert\n");
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log(" also create an 'assert' cell that checks if trigger is always low.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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if (args.size() > 1 && args[1] == "-equiv") {
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create_miter_equiv(this, args, design);
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return;
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}
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log_cmd_error("Missing mode parameter!\n");
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}
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} MiterPass;
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