mirror of https://github.com/YosysHQ/yosys.git
Rename shregmap -tech xilinx -> xilinx_dynamic
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7b186740d3
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@ -93,12 +93,12 @@ struct ShregmapTechGreenpak4 : ShregmapTech
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}
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};
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struct ShregmapTechXilinx7 : ShregmapTech
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struct ShregmapTechXilinx7Dynamic : ShregmapTech
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{
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dict<SigBit, std::tuple<Cell*,int,int>> sigbit_to_shiftx_offset;
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const ShregmapOptions &opts;
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ShregmapTechXilinx7(const ShregmapOptions &opts) : opts(opts) {}
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ShregmapTechXilinx7Dynamic(const ShregmapOptions &opts) : opts(opts) {}
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virtual void init(const Module* module, const SigMap &sigmap) override
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{
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@ -660,11 +660,11 @@ struct ShregmapPass : public Pass {
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opts.zinit = true;
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opts.tech = new ShregmapTechGreenpak4;
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}
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else if (tech == "xilinx") {
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else if (tech == "xilinx_dynamic") {
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opts.init = true;
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opts.params = true;
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enpol = "any_or_none";
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opts.tech = new ShregmapTechXilinx7(opts);
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opts.tech = new ShregmapTechXilinx7Dynamic(opts);
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} else {
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argidx--;
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break;
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@ -263,8 +263,8 @@ struct SynthXilinxPass : public ScriptPass
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// shregmap operates on bit-level flops, not word-level,
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// so break those down here
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run("simplemap t:$dff t:$dffe", "(skip if '-nosrl')");
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// shregmap with '-tech xilinx' infers variable length shift regs
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run("shregmap -tech xilinx -minlen 3", "(skip if '-nosrl')");
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// shregmap to infer variable length shift regs
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run("shregmap -tech xilinx_dynamic -minlen 3", "(skip if '-nosrl')");
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}
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std::string techmap_files = " -map +/techmap.v";
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