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Merge remote-tracking branch 'origin/master' into xaig

This commit is contained in:
Eddie Hung 2019-04-15 21:56:45 -07:00
parent fecafb2207 dca45c0888
commit 0391499e46
3 changed files with 5 additions and 6 deletions
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4
README.md
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@ -312,10 +312,10 @@ Verilog Attributes and non-standard features
passes to identify input and output ports of cells. The Verilog backend
also does not output blackbox modules on default.
- The ``dynports'' attribute is used by the Verilog front-end to mark modules
- The ``dynports`` attribute is used by the Verilog front-end to mark modules
that have ports with a width that depends on a parameter.
- The ``hdlname'' attribute is used by some passes to document the original
- The ``hdlname`` attribute is used by some passes to document the original
(HDL) name of a module when renaming a module.
- The ``keep`` attribute on cells and wires is used to mark objects that should

2
passes/proc/proc_rmdead.cc
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@ -34,7 +34,7 @@ void proc_rmdead(RTLIL::SwitchRule *sw, int &counter)
for (size_t i = 0; i < sw->cases.size(); i++)
{
bool is_default = GetSize(sw->cases[i]->compare) == 0 || GetSize(sw->signal) == 0;
bool is_default = GetSize(sw->cases[i]->compare) == 0 && (!pool.empty() || GetSize(sw->signal) == 0);
for (size_t j = 0; j < sw->cases[i]->compare.size(); j++) {
RTLIL::SigSpec sig = sw->cases[i]->compare[j];

5
tests/various/muxcover.ys
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@ -8,13 +8,12 @@ read_verilog -formal <<EOT
3'b?1?: Y = B;
3'b1??: Y = C;
3'b000: Y = D;
default: Y = 'bx;
endcase
endmodule
EOT
## Example usage for "pmuxtree" and "muxcover"
## Examle usage for "pmuxtree" and "muxcover"
proc
pmuxtree
@ -36,7 +35,7 @@ read_verilog -formal <<EOT
3'b010: Y = B;
3'b100: Y = C;
3'b000: Y = D;
default: Y = 'bx;
default: Y = 'bx;
endcase
endmodule
EOT