mirror of https://github.com/YosysHQ/yosys.git
Forgot backslashes
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9bfcd80063
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fecafb2207
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@ -477,7 +477,7 @@ next_line:
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RTLIL::Wire* wire = outputs[variable];
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log_assert(wire);
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log_assert(wire->port_output);
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if (escaped_s.in("__dummy_o__", "__const0__", "__const1__")) {
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if (escaped_s.in("\\__dummy_o__", "\\__const0__", "\\__const1__")) {
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wire->port_output = false;
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continue;
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}
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