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Handle __dummy_o__ and __const[01]__ in read_aiger not abc

This commit is contained in:
Eddie Hung 2019-04-12 18:21:16 -07:00
parent 482a60825b
commit 9bfcd80063
2 changed files with 8 additions and 18 deletions
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4
frontends/aiger/aigerparse.cc
View File

@ -477,6 +477,10 @@ next_line:
RTLIL::Wire* wire = outputs[variable];
log_assert(wire);
log_assert(wire->port_output);
if (escaped_s.in("__dummy_o__", "__const0__", "__const1__")) {
wire->port_output = false;
continue;
}
if (index == 0) {
// Cope with the fact that a CO might be identical

22
passes/techmap/abc9.cc
View File

@ -546,11 +546,10 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
output_bits.insert({wire, i});
}
else {
if (w->name.in("\\__dummy_o__", "\\__const0__", "\\__const1__")) {
//log("Don't call ABC as there is nothing to map.\n");
//goto cleanup;
continue;
}
//if (w->name == "\\__dummy_o__") {
// log("Don't call ABC as there is nothing to map.\n");
// goto cleanup;
//}
// Attempt another wideports_split here because there
// exists the possibility that different bits of a port
@ -875,19 +874,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
RTLIL::Wire *w = it.second;
if (!w->port_input && !w->port_output)
continue;
if (w->name == "\\__const0__") {
log_assert(w->port_output);
module->connect(w, RTLIL::S0);
continue;
}
if (w->name == "\\__const1__") {
log_assert(w->port_output);
module->connect(w, RTLIL::S1);
continue;
}
if (w->name == "\\__dummy_o__")
continue;
RTLIL::Wire *wire = module->wire(w->name);
RTLIL::Wire *remap_wire = module->wire(remap_name(w->name));
RTLIL::SigSpec signal;