mirror of https://github.com/YosysHQ/yosys.git
Do not the 'z' modifier in format string (another win32 fix)
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8263f6a74a
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@ -267,7 +267,7 @@ void AstNode::dumpAst(FILE *f, std::string indent)
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bits[i-1] == RTLIL::S1 ? '1' :
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bits[i-1] == RTLIL::Sx ? 'x' :
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bits[i-1] == RTLIL::Sz ? 'z' : '?');
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fprintf(f, "'(%zd)", bits.size());
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fprintf(f, "'(%d)", GetSize(bits));
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}
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if (is_input)
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fprintf(f, " input");
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@ -471,7 +471,7 @@ void AstNode::dumpVlog(FILE *f, std::string indent)
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else if (bits.size() == 32)
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fprintf(f, "%d", RTLIL::Const(bits).as_int());
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else
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fprintf(f, "%zd'b %s", bits.size(), RTLIL::Const(bits).as_string().c_str());
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fprintf(f, "%d'b %s", GetSize(bits), RTLIL::Const(bits).as_string().c_str());
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break;
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case AST_REALVALUE:
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@ -239,7 +239,7 @@ struct FsmExpand
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if (merged_set.size() > 0 && !already_optimized)
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FsmData::optimize_fsm(fsm_cell, module);
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log(" merged %zd cells into FSM.\n", merged_set.size());
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log(" merged %d cells into FSM.\n", GetSize(merged_set));
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}
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};
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@ -41,9 +41,9 @@ static void fm_set_fsm_print(RTLIL::Cell *cell, RTLIL::Module *module, FsmData &
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prefix, RTLIL::unescape_id(module->name).c_str());
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fprintf(f, "set_fsm_encoding {");
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for (size_t i = 0; i < fsm_data.state_table.size(); i++) {
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fprintf(f, " s%zd=2#", i);
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for (int j = int(fsm_data.state_table[i].bits.size())-1; j >= 0; j--)
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for (int i = 0; i < GetSize(fsm_data.state_table); i++) {
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fprintf(f, " s%d=2#", i);
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for (int j = GetSize(fsm_data.state_table[i].bits)-1; j >= 0; j--)
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fprintf(f, "%c", fsm_data.state_table[i].bits[j] == RTLIL::State::S1 ? '1' : '0');
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}
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fprintf(f, " } -name {%s_%s} {%s:/WORK/%s}\n",
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@ -281,7 +281,7 @@ void hierarchy(RTLIL::Design *design, RTLIL::Module *top, bool purge_lib, bool f
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delete mod;
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}
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log("Removed %zd unused modules.\n", del_modules.size());
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log("Removed %d unused modules.\n", GetSize(del_modules));
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}
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bool set_keep_assert(std::map<RTLIL::Module*, bool> &cache, RTLIL::Module *mod)
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@ -174,12 +174,12 @@ struct OptMuxtreeWorker
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for (auto &mi : mux2info)
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{
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std::vector<int> live_ports;
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for (size_t port_idx = 0; port_idx < mi.ports.size(); port_idx++) {
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for (int port_idx = 0; port_idx < GetSize(mi.ports); port_idx++) {
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portinfo_t &pi = mi.ports[port_idx];
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if (pi.enabled) {
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live_ports.push_back(port_idx);
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} else {
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log(" dead port %zd/%zd on %s %s.\n", port_idx+1, mi.ports.size(),
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log(" dead port %d/%d on %s %s.\n", port_idx+1, GetSize(mi.ports),
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mi.cell->type.c_str(), mi.cell->name.c_str());
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removed_count++;
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}
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