mirror of https://github.com/YosysHQ/yosys.git
Improve log messages in equiv_make
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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@ -260,11 +260,11 @@ struct EquivMakeWorker
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for (int i = 0; i < wire->width; i++) {
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if (undriven_bits.count(assign_map(SigBit(gold_wire, i)))) {
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log(" Skipping signal bit %d: undriven on gold side.\n", i);
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log(" Skipping signal bit %s [%d]: undriven on gold side.\n", id2cstr(gold_wire->name), i);
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continue;
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}
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if (undriven_bits.count(assign_map(SigBit(gate_wire, i)))) {
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log(" Skipping signal bit %d: undriven on gate side.\n", i);
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log(" Skipping signal bit %s [%d]: undriven on gate side.\n", id2cstr(gate_wire->name), i);
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continue;
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}
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equiv_mod->addEquiv(NEW_ID, SigSpec(gold_wire, i), SigSpec(gate_wire, i), SigSpec(wire, i));
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