mirror of https://github.com/YosysHQ/yosys.git
Added hierarchy -auto-top
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@ -321,6 +321,17 @@ bool set_keep_assert(std::map<RTLIL::Module*, bool> &cache, RTLIL::Module *mod)
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return cache[mod];
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}
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int find_top_mod_score(Design *design, Module *module, dict<Module*, int> &db)
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{
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if (db.count(module) == 0) {
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db[module] = 0;
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for (auto cell : module->cells())
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if (design->module(cell->type))
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db[module] = std::max(db[module], find_top_mod_score(design, design->module(cell->type), db) + 1);
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}
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return db.at(module);
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}
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struct HierarchyPass : public Pass {
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HierarchyPass() : Pass("hierarchy", "check, expand and clean up design hierarchy") { }
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virtual void help()
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@ -365,6 +376,9 @@ struct HierarchyPass : public Pass {
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log(" specified top module. otherwise a module with the 'top' attribute set\n");
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log(" will implicitly be used as top module, if such a module exists.\n");
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log("\n");
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log(" -auto-top\n");
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log(" automatically determine the top of the design hierarchy and mark it.\n");
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log("\n");
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log("In -generate mode this pass generates blackbox modules for the given cell\n");
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log("types (wildcards supported). For this the design is searched for cells that\n");
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log("match the given types and then the given port declarations are used to\n");
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@ -391,6 +405,7 @@ struct HierarchyPass : public Pass {
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RTLIL::Module *top_mod = NULL;
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std::vector<std::string> libdirs;
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bool auto_top_mode = false;
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bool generate_mode = false;
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bool keep_positionals = false;
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bool nokeep_asserts = false;
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@ -472,6 +487,10 @@ struct HierarchyPass : public Pass {
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log_cmd_error("Module `%s' not found!\n", args[argidx].c_str());
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continue;
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}
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if (args[argidx] == "-auto-top") {
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auto_top_mode = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design, false);
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@ -483,11 +502,24 @@ struct HierarchyPass : public Pass {
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log_push();
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if (top_mod == NULL)
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if (top_mod == nullptr)
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for (auto &mod_it : design->modules_)
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if (mod_it.second->get_bool_attribute("\\top"))
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top_mod = mod_it.second;
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if (top_mod == nullptr && auto_top_mode) {
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log_header("Finding top of design hierarchy..\n");
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dict<Module*, int> db;
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for (Module *mod : design->modules()) {
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int score = find_top_mod_score(design, mod, db);
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log("root of %3d design levels: %-20s\n", score, log_id(mod));
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if (!top_mod || score > db[top_mod])
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top_mod = mod;
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}
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if (top_mod != nullptr)
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log("Automatically selected %s as design top module.\n", log_id(top_mod));
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}
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bool did_something = true;
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while (did_something)
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{
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