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Catch constants assigned to cell outputs in "flatten"

This commit is contained in:
Clifford Wolf 2015-02-21 11:21:28 +01:00
parent d5ce9a32ef
commit f778a4081c
1 changed files with 6 additions and 0 deletions
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6
passes/techmap/techmap.cc
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@ -66,6 +66,7 @@ struct TechmapWorker
std::map<std::pair<RTLIL::IdString, std::map<RTLIL::IdString, RTLIL::Const>>, RTLIL::Module*> techmap_cache;
std::map<RTLIL::Module*, bool> techmap_do_cache;
std::set<RTLIL::Module*, RTLIL::IdString::compare_ptr_by_name<RTLIL::Module>> module_queue;
dict<Module*, SigMap> sigmaps;
struct TechmapWireData {
RTLIL::Wire *wire;
@ -235,6 +236,11 @@ struct TechmapWorker
if (flatten_mode) {
// more conservative approach:
// connect internal and external wires
if (sigmaps.count(module) == 0)
sigmaps[module].set(module);
if (sigmaps.at(module)(c.first).has_const())
log_error("Mismatch in directionality for cell port %s.%s.%s: %s <= %s\n",
log_id(module), log_id(cell), log_id(it.first), log_signal(c.first), log_signal(c.second));
module->connect(c);
} else {
// approach that yields nicer outputs: