mirror of https://github.com/YosysHQ/yosys.git
More "freduce" related fixes and improvements
This commit is contained in:
Clifford Wolf
parent
ced4d7b321
commit
0759c97748
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@ -38,6 +38,7 @@ struct equiv_bit_t
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{
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int depth;
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bool inverted;
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RTLIL::Cell *drv;
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RTLIL::SigBit bit;
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bool operator<(const equiv_bit_t &other) const {
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@ -45,6 +46,8 @@ struct equiv_bit_t
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return depth < other.depth;
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if (inverted != other.inverted)
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return inverted < other.inverted;
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if (drv != other.drv)
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return drv < other.drv;
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return bit < other.bit;
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}
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};
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@ -216,7 +219,7 @@ struct PerformReduction
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out_inverted = std::vector<bool>(sat_out.size(), false);
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}
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void analyze(std::vector<std::vector<equiv_bit_t>> &results, std::vector<int> &bucket, int level)
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void analyze(std::vector<std::set<int>> &results, std::map<int, int> &results_map, std::vector<int> &bucket, int level)
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{
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if (bucket.size() <= 1)
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return;
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@ -233,10 +236,9 @@ struct PerformReduction
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std::vector<int> modelVars = sat_out;
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std::vector<bool> model;
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if (verbose_level >= 2) {
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modelVars.insert(modelVars.end(), sat_def.begin(), sat_def.end());
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modelVars.insert(modelVars.end(), sat_def.begin(), sat_def.end());
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if (verbose_level >= 2)
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modelVars.insert(modelVars.end(), sat_pi.begin(), sat_pi.end());
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}
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if (ez.solve(modelVars, model, ez.expression(ezSAT::OpOr, sat_list), ez.expression(ezSAT::OpOr, sat_inv_list)))
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{
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@ -248,11 +250,17 @@ struct PerformReduction
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out_inverted.at(idx) ? "~" : "", log_signal(out_bits[idx]));
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}
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std::vector<int> buckets[2];
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for (int idx : bucket)
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buckets[model[idx] ? 1 : 0].push_back(idx);
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analyze(results, buckets[0], level+1);
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analyze(results, buckets[1], level+1);
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std::vector<int> buckets_a;
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std::vector<int> buckets_b;
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for (int idx : bucket) {
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if (!model[sat_out.size() + idx] || model[idx])
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buckets_a.push_back(idx);
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if (!model[sat_out.size() + idx] || !model[idx])
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buckets_b.push_back(idx);
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}
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analyze(results, results_map, buckets_a, level+1);
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analyze(results, results_map, buckets_b, level+1);
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}
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else
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{
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@ -263,16 +271,58 @@ struct PerformReduction
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log("\n");
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}
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std::vector<equiv_bit_t> result;
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int result_idx = -1;
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for (int idx : bucket) {
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if (results_map.count(idx) == 0)
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continue;
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if (result_idx == -1) {
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result_idx = results_map.at(idx);
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continue;
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}
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int result_idx2 = results_map.at(idx);
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results[result_idx].insert(results[result_idx2].begin(), results[result_idx2].end());
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for (int idx2 : results[result_idx2])
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results_map[idx2] = result_idx;
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results[result_idx2].clear();
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}
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if (result_idx == -1) {
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result_idx = results.size();
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results.push_back(std::set<int>());
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}
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results[result_idx].insert(bucket.begin(), bucket.end());
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}
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}
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void analyze(std::vector<std::vector<equiv_bit_t>> &results)
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{
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std::vector<int> bucket;
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for (size_t i = 0; i < sat_out.size(); i++)
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bucket.push_back(i);
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std::vector<std::set<int>> results_buf;
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std::map<int, int> results_map;
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analyze(results_buf, results_map, bucket, 1);
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for (auto &r : results_buf)
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{
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if (r.size() <= 1)
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continue;
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std::vector<equiv_bit_t> result;
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for (int idx : r) {
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equiv_bit_t bit;
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bit.depth = out_depth[idx];
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bit.inverted = out_inverted[idx];
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bit.drv = drivers.count(out_bits[idx]) ? drivers.at(out_bits[idx]).first : NULL;
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bit.bit = out_bits[idx];
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result.push_back(bit);
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}
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std::sort(result.begin(), result.end());
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if (result.front().inverted)
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for (auto &bit : result)
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bit.inverted = !bit.inverted;
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@ -287,14 +337,6 @@ struct PerformReduction
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results.push_back(result);
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}
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}
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void analyze(std::vector<std::vector<equiv_bit_t>> &results)
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{
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std::vector<int> bucket;
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for (size_t i = 0; i < sat_out.size(); i++)
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bucket.push_back(i);
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analyze(results, bucket, 1);
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}
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};
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struct FreduceHelper
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@ -318,6 +360,9 @@ struct FreduceHelper
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ct.setup_stdcells();
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std::vector<std::set<RTLIL::SigBit>> batches;
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for (auto &it : module->wires)
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if (it.second->port_input)
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batches.push_back(sigmap(it.second).to_sigbit_set());
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for (auto &it : module->cells) {
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if (ct.cell_known(it.second->type)) {
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std::set<RTLIL::SigBit> inputs, outputs;
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@ -426,7 +471,10 @@ struct FreducePass : public Pass {
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log("\n");
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log("This pass performs functional reduction in the circuit. I.e. if two nodes are\n");
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log("equivialent, they are merged to one node and one of the redundant drivers is\n");
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log("removed.\n");
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log("unconnected. A subsequent call to 'clean' will remove the redundant drivers.\n");
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log("\n");
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log("This pass is undef-aware, i.e. it considers don't-care values for detecting\n");
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log("equivialent nodes.\n");
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log("\n");
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log(" -v, -vv\n");
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log(" enable verbose or very verbose output\n");
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