mirror of https://github.com/YosysHQ/yosys.git
Added recursion support to techmap
This commit is contained in:
Clifford Wolf
parent
aeb36b0b8b
commit
d3dc22a90f
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@ -50,317 +50,320 @@ static void apply_prefix(std::string prefix, RTLIL::SigSpec &sig, RTLIL::Module
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}
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}
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std::map<std::string, void(*)(RTLIL::Module*, RTLIL::Cell*)> simplemap_mappers;
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std::map<std::pair<RTLIL::IdString, std::map<RTLIL::IdString, RTLIL::Const>>, RTLIL::Module*> techmap_cache;
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std::map<RTLIL::Module*, bool> techmap_do_cache;
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struct TechmapWireData {
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RTLIL::Wire *wire;
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RTLIL::SigSpec value;
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};
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typedef std::map<std::string, std::vector<TechmapWireData>> TechmapWires;
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static TechmapWires techmap_find_special_wires(RTLIL::Module *module)
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struct TechmapWorker
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{
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TechmapWires result;
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std::map<std::string, void(*)(RTLIL::Module*, RTLIL::Cell*)> simplemap_mappers;
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std::map<std::pair<RTLIL::IdString, std::map<RTLIL::IdString, RTLIL::Const>>, RTLIL::Module*> techmap_cache;
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std::map<RTLIL::Module*, bool> techmap_do_cache;
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if (module == NULL)
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return result;
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struct TechmapWireData {
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RTLIL::Wire *wire;
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RTLIL::SigSpec value;
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};
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for (auto &it : module->wires) {
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const char *p = it.first.c_str();
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if (*p == '$')
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continue;
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typedef std::map<std::string, std::vector<TechmapWireData>> TechmapWires;
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const char *q = strrchr(p+1, '.');
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p = q ? q : p+1;
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if (!strncmp(p, "_TECHMAP_", 9)) {
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TechmapWireData record;
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record.wire = it.second;
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record.value = it.second;
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result[p].push_back(record);
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it.second->attributes["\\keep"] = RTLIL::Const(1);
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it.second->attributes["\\_techmap_special_"] = RTLIL::Const(1);
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}
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}
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if (!result.empty()) {
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SigMap sigmap(module);
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for (auto &it1 : result)
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for (auto &it2 : it1.second)
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sigmap.apply(it2.value);
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}
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return result;
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}
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static void techmap_module_worker(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Cell *cell, RTLIL::Module *tpl, bool flatten_mode)
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{
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log("Mapping `%s.%s' using `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(tpl->name));
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if (tpl->memories.size() != 0)
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log_error("Technology map yielded memories -> this is not supported.\n");
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if (tpl->processes.size() != 0)
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log_error("Technology map yielded processes -> this is not supported.\n");
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std::map<RTLIL::IdString, RTLIL::IdString> positional_ports;
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for (auto &it : tpl->wires) {
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if (it.second->port_id > 0)
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positional_ports[stringf("$%d", it.second->port_id)] = it.first;
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RTLIL::Wire *w = new RTLIL::Wire(*it.second);
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apply_prefix(cell->name, w->name);
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w->port_input = false;
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w->port_output = false;
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w->port_id = 0;
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if (it.second->get_bool_attribute("\\_techmap_special_"))
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w->attributes.clear();
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module->wires[w->name] = w;
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design->select(module, w);
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}
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SigMap port_signal_map;
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for (auto &it : cell->connections) {
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RTLIL::IdString portname = it.first;
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if (positional_ports.count(portname) > 0)
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portname = positional_ports.at(portname);
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if (tpl->wires.count(portname) == 0 || tpl->wires.at(portname)->port_id == 0) {
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if (portname.substr(0, 1) == "$")
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log_error("Can't map port `%s' of cell `%s' to template `%s'!\n", portname.c_str(), cell->name.c_str(), tpl->name.c_str());
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continue;
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}
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RTLIL::Wire *w = tpl->wires.at(portname);
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RTLIL::SigSig c;
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if (w->port_output) {
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c.first = it.second;
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c.second = RTLIL::SigSpec(w);
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apply_prefix(cell->name, c.second, module);
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} else {
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c.first = RTLIL::SigSpec(w);
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c.second = it.second;
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apply_prefix(cell->name, c.first, module);
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}
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if (c.second.width > c.first.width)
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c.second.remove(c.first.width, c.second.width - c.first.width);
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if (c.second.width < c.first.width)
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c.second.append(RTLIL::SigSpec(RTLIL::State::S0, c.first.width - c.second.width));
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assert(c.first.width == c.second.width);
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#if 0
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// more conservative approach:
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// connect internal and external wires
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module->connections.push_back(c);
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#else
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// approach that yields nicer outputs:
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// replace internal wires that are connected to external wires
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if (w->port_output)
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port_signal_map.add(c.second, c.first);
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else
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port_signal_map.add(c.first, c.second);
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#endif
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}
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for (auto &it : tpl->cells) {
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RTLIL::Cell *c = new RTLIL::Cell(*it.second);
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if (!flatten_mode && c->type.substr(0, 2) == "\\$")
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c->type = c->type.substr(1);
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apply_prefix(cell->name, c->name);
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for (auto &it2 : c->connections) {
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apply_prefix(cell->name, it2.second, module);
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port_signal_map.apply(it2.second);
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}
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module->cells[c->name] = c;
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design->select(module, c);
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}
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for (auto &it : tpl->connections) {
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RTLIL::SigSig c = it;
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apply_prefix(cell->name, c.first, module);
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apply_prefix(cell->name, c.second, module);
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port_signal_map.apply(c.first);
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port_signal_map.apply(c.second);
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module->connections.push_back(c);
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}
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module->cells.erase(cell->name);
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delete cell;
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}
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static bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, std::set<RTLIL::Cell*> &handled_cells,
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const std::map<RTLIL::IdString, std::set<RTLIL::IdString>> &celltypeMap, bool flatten_mode)
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{
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if (!design->selected(module))
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return false;
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bool log_continue = false;
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bool did_something = false;
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std::vector<std::string> cell_names;
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for (auto &cell_it : module->cells)
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cell_names.push_back(cell_it.first);
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for (auto &cell_name : cell_names)
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TechmapWires techmap_find_special_wires(RTLIL::Module *module)
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{
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if (module->cells.count(cell_name) == 0)
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continue;
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TechmapWires result;
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RTLIL::Cell *cell = module->cells[cell_name];
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if (module == NULL)
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return result;
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if (!design->selected(module, cell) || handled_cells.count(cell) > 0)
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continue;
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for (auto &it : module->wires) {
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const char *p = it.first.c_str();
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if (*p == '$')
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continue;
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if (celltypeMap.count(cell->type) == 0)
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continue;
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const char *q = strrchr(p+1, '.');
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p = q ? q : p+1;
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for (auto &tpl_name : celltypeMap.at(cell->type))
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{
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std::string derived_name = tpl_name;
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RTLIL::Module *tpl = map->modules[tpl_name];
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std::map<RTLIL::IdString, RTLIL::Const> parameters = cell->parameters;
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if (!flatten_mode)
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{
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if (tpl->get_bool_attribute("\\techmap_simplemap")) {
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log("Mapping %s.%s (%s) with simplemap.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
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if (simplemap_mappers.count(cell->type) == 0)
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log_error("No simplemap mapper for cell type %s found!\n", RTLIL::id2cstr(cell->type));
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simplemap_mappers.at(cell->type)(module, cell);
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module->cells.erase(cell->name);
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delete cell;
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cell = NULL;
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did_something = true;
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break;
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}
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for (auto conn : cell->connections) {
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if (conn.first.substr(0, 1) == "$")
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continue;
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if (tpl->wires.count(conn.first) > 0 && tpl->wires.at(conn.first)->port_id > 0)
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continue;
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if (!conn.second.is_fully_const() || parameters.count(conn.first) > 0 || tpl->avail_parameters.count(conn.first) == 0)
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goto next_tpl;
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parameters[conn.first] = conn.second.as_const();
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}
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if (0) {
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next_tpl:
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continue;
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}
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if (tpl->avail_parameters.count("\\_TECHMAP_CELLTYPE_") != 0)
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parameters["\\_TECHMAP_CELLTYPE_"] = RTLIL::unescape_id(cell->type);
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if (!strncmp(p, "_TECHMAP_", 9)) {
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TechmapWireData record;
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record.wire = it.second;
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record.value = it.second;
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result[p].push_back(record);
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it.second->attributes["\\keep"] = RTLIL::Const(1);
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it.second->attributes["\\_techmap_special_"] = RTLIL::Const(1);
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}
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}
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std::pair<RTLIL::IdString, std::map<RTLIL::IdString, RTLIL::Const>> key(tpl_name, parameters);
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if (techmap_cache.count(key) > 0) {
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tpl = techmap_cache[key];
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if (!result.empty()) {
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SigMap sigmap(module);
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for (auto &it1 : result)
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for (auto &it2 : it1.second)
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sigmap.apply(it2.value);
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}
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return result;
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}
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void techmap_module_worker(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Cell *cell, RTLIL::Module *tpl, bool flatten_mode)
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{
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log("Mapping `%s.%s' using `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(tpl->name));
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if (tpl->memories.size() != 0)
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log_error("Technology map yielded memories -> this is not supported.\n");
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if (tpl->processes.size() != 0)
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log_error("Technology map yielded processes -> this is not supported.\n");
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std::map<RTLIL::IdString, RTLIL::IdString> positional_ports;
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for (auto &it : tpl->wires) {
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if (it.second->port_id > 0)
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positional_ports[stringf("$%d", it.second->port_id)] = it.first;
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RTLIL::Wire *w = new RTLIL::Wire(*it.second);
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apply_prefix(cell->name, w->name);
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w->port_input = false;
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w->port_output = false;
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w->port_id = 0;
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if (it.second->get_bool_attribute("\\_techmap_special_"))
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w->attributes.clear();
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module->wires[w->name] = w;
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design->select(module, w);
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}
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SigMap port_signal_map;
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for (auto &it : cell->connections) {
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RTLIL::IdString portname = it.first;
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if (positional_ports.count(portname) > 0)
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portname = positional_ports.at(portname);
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if (tpl->wires.count(portname) == 0 || tpl->wires.at(portname)->port_id == 0) {
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if (portname.substr(0, 1) == "$")
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log_error("Can't map port `%s' of cell `%s' to template `%s'!\n", portname.c_str(), cell->name.c_str(), tpl->name.c_str());
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continue;
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}
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RTLIL::Wire *w = tpl->wires.at(portname);
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RTLIL::SigSig c;
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if (w->port_output) {
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c.first = it.second;
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c.second = RTLIL::SigSpec(w);
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apply_prefix(cell->name, c.second, module);
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} else {
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if (cell->parameters.size() != 0) {
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derived_name = tpl->derive(map, parameters);
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tpl = map->modules[derived_name];
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log_continue = true;
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}
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techmap_cache[key] = tpl;
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c.first = RTLIL::SigSpec(w);
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c.second = it.second;
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apply_prefix(cell->name, c.first, module);
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}
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if (c.second.width > c.first.width)
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c.second.remove(c.first.width, c.second.width - c.first.width);
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if (c.second.width < c.first.width)
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c.second.append(RTLIL::SigSpec(RTLIL::State::S0, c.first.width - c.second.width));
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assert(c.first.width == c.second.width);
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#if 0
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// more conservative approach:
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// connect internal and external wires
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module->connections.push_back(c);
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#else
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// approach that yields nicer outputs:
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// replace internal wires that are connected to external wires
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if (w->port_output)
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port_signal_map.add(c.second, c.first);
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else
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port_signal_map.add(c.first, c.second);
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#endif
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}
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if (flatten_mode)
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techmap_do_cache[tpl] = true;
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for (auto &it : tpl->cells) {
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RTLIL::Cell *c = new RTLIL::Cell(*it.second);
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if (!flatten_mode && c->type.substr(0, 2) == "\\$")
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c->type = c->type.substr(1);
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apply_prefix(cell->name, c->name);
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for (auto &it2 : c->connections) {
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apply_prefix(cell->name, it2.second, module);
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port_signal_map.apply(it2.second);
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}
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module->cells[c->name] = c;
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design->select(module, c);
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}
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if (techmap_do_cache.count(tpl) == 0)
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for (auto &it : tpl->connections) {
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RTLIL::SigSig c = it;
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apply_prefix(cell->name, c.first, module);
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apply_prefix(cell->name, c.second, module);
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port_signal_map.apply(c.first);
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port_signal_map.apply(c.second);
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module->connections.push_back(c);
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}
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module->cells.erase(cell->name);
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delete cell;
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}
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bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, std::set<RTLIL::Cell*> &handled_cells,
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const std::map<RTLIL::IdString, std::set<RTLIL::IdString>> &celltypeMap, bool flatten_mode)
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{
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if (!design->selected(module))
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return false;
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bool log_continue = false;
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bool did_something = false;
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std::vector<std::string> cell_names;
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for (auto &cell_it : module->cells)
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cell_names.push_back(cell_it.first);
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for (auto &cell_name : cell_names)
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{
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if (module->cells.count(cell_name) == 0)
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continue;
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RTLIL::Cell *cell = module->cells[cell_name];
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if (!design->selected(module, cell) || handled_cells.count(cell) > 0)
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continue;
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if (celltypeMap.count(cell->type) == 0)
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continue;
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for (auto &tpl_name : celltypeMap.at(cell->type))
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{
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bool keep_running = true;
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techmap_do_cache[tpl] = true;
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std::string derived_name = tpl_name;
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RTLIL::Module *tpl = map->modules[tpl_name];
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std::map<RTLIL::IdString, RTLIL::Const> parameters = cell->parameters;
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while (keep_running)
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if (!flatten_mode)
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{
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TechmapWires twd = techmap_find_special_wires(tpl);
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keep_running = false;
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if (tpl->get_bool_attribute("\\techmap_simplemap")) {
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log("Mapping %s.%s (%s) with simplemap.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
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if (simplemap_mappers.count(cell->type) == 0)
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log_error("No simplemap mapper for cell type %s found!\n", RTLIL::id2cstr(cell->type));
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simplemap_mappers.at(cell->type)(module, cell);
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module->cells.erase(cell->name);
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delete cell;
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cell = NULL;
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did_something = true;
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break;
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}
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for (auto &it : twd["_TECHMAP_FAIL_"]) {
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RTLIL::SigSpec value = it.value;
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if (value.is_fully_const() && value.as_bool()) {
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log("Not using module `%s' from techmap as it contains a %s marker wire with non-zero value %s.\n",
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derived_name.c_str(), RTLIL::id2cstr(it.wire->name), log_signal(value));
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techmap_do_cache[tpl] = false;
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for (auto conn : cell->connections) {
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if (conn.first.substr(0, 1) == "$")
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continue;
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if (tpl->wires.count(conn.first) > 0 && tpl->wires.at(conn.first)->port_id > 0)
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continue;
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if (!conn.second.is_fully_const() || parameters.count(conn.first) > 0 || tpl->avail_parameters.count(conn.first) == 0)
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goto next_tpl;
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parameters[conn.first] = conn.second.as_const();
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}
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||||
if (0) {
|
||||
next_tpl:
|
||||
continue;
|
||||
}
|
||||
|
||||
if (tpl->avail_parameters.count("\\_TECHMAP_CELLTYPE_") != 0)
|
||||
parameters["\\_TECHMAP_CELLTYPE_"] = RTLIL::unescape_id(cell->type);
|
||||
}
|
||||
|
||||
std::pair<RTLIL::IdString, std::map<RTLIL::IdString, RTLIL::Const>> key(tpl_name, parameters);
|
||||
if (techmap_cache.count(key) > 0) {
|
||||
tpl = techmap_cache[key];
|
||||
} else {
|
||||
if (cell->parameters.size() != 0) {
|
||||
derived_name = tpl->derive(map, parameters);
|
||||
tpl = map->modules[derived_name];
|
||||
log_continue = true;
|
||||
}
|
||||
techmap_cache[key] = tpl;
|
||||
}
|
||||
|
||||
if (flatten_mode)
|
||||
techmap_do_cache[tpl] = true;
|
||||
|
||||
if (techmap_do_cache.count(tpl) == 0)
|
||||
{
|
||||
bool keep_running = true;
|
||||
techmap_do_cache[tpl] = true;
|
||||
|
||||
while (keep_running)
|
||||
{
|
||||
TechmapWires twd = techmap_find_special_wires(tpl);
|
||||
keep_running = false;
|
||||
|
||||
for (auto &it : twd["_TECHMAP_FAIL_"]) {
|
||||
RTLIL::SigSpec value = it.value;
|
||||
if (value.is_fully_const() && value.as_bool()) {
|
||||
log("Not using module `%s' from techmap as it contains a %s marker wire with non-zero value %s.\n",
|
||||
derived_name.c_str(), RTLIL::id2cstr(it.wire->name), log_signal(value));
|
||||
techmap_do_cache[tpl] = false;
|
||||
}
|
||||
}
|
||||
|
||||
if (!techmap_do_cache[tpl])
|
||||
break;
|
||||
|
||||
for (auto &it : twd)
|
||||
{
|
||||
if (it.first.substr(0, 12) != "_TECHMAP_DO_" || it.second.empty())
|
||||
continue;
|
||||
|
||||
auto &data = it.second.front();
|
||||
|
||||
if (!data.value.is_fully_const())
|
||||
log_error("Techmap yielded config wire %s with non-const value %s.\n", RTLIL::id2cstr(data.wire->name), log_signal(data.value));
|
||||
|
||||
tpl->wires.erase(data.wire->name);
|
||||
const char *p = data.wire->name.c_str();
|
||||
const char *q = strrchr(p+1, '.');
|
||||
q = q ? q : p+1;
|
||||
|
||||
assert(!strncmp(q, "_TECHMAP_DO_", 12));
|
||||
std::string new_name = data.wire->name.substr(0, q-p) + "_TECHMAP_DONE_" + data.wire->name.substr(q-p+12);
|
||||
while (tpl->wires.count(new_name))
|
||||
new_name += "_";
|
||||
data.wire->name = new_name;
|
||||
tpl->add(data.wire);
|
||||
|
||||
std::string cmd_string = data.value.as_const().decode_string();
|
||||
|
||||
RTLIL::Selection tpl_mod_sel(false);
|
||||
tpl_mod_sel.select(tpl);
|
||||
map->selection_stack.push_back(tpl_mod_sel);
|
||||
Pass::call(map, cmd_string);
|
||||
map->selection_stack.pop_back();
|
||||
|
||||
keep_running = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (!techmap_do_cache[tpl])
|
||||
break;
|
||||
|
||||
for (auto &it : twd)
|
||||
{
|
||||
if (it.first.substr(0, 12) != "_TECHMAP_DO_" || it.second.empty())
|
||||
continue;
|
||||
|
||||
auto &data = it.second.front();
|
||||
|
||||
if (!data.value.is_fully_const())
|
||||
log_error("Techmap yielded config wire %s with non-const value %s.\n", RTLIL::id2cstr(data.wire->name), log_signal(data.value));
|
||||
|
||||
tpl->wires.erase(data.wire->name);
|
||||
const char *p = data.wire->name.c_str();
|
||||
const char *q = strrchr(p+1, '.');
|
||||
q = q ? q : p+1;
|
||||
|
||||
assert(!strncmp(q, "_TECHMAP_DO_", 12));
|
||||
std::string new_name = data.wire->name.substr(0, q-p) + "_TECHMAP_DONE_" + data.wire->name.substr(q-p+12);
|
||||
while (tpl->wires.count(new_name))
|
||||
new_name += "_";
|
||||
data.wire->name = new_name;
|
||||
tpl->add(data.wire);
|
||||
|
||||
std::string cmd_string = data.value.as_const().decode_string();
|
||||
|
||||
RTLIL::Selection tpl_mod_sel(false);
|
||||
tpl_mod_sel.select(tpl);
|
||||
map->selection_stack.push_back(tpl_mod_sel);
|
||||
Pass::call(map, cmd_string);
|
||||
map->selection_stack.pop_back();
|
||||
|
||||
keep_running = true;
|
||||
break;
|
||||
TechmapWires twd = techmap_find_special_wires(tpl);
|
||||
for (auto &it : twd) {
|
||||
if (it.first != "_TECHMAP_FAIL_" && it.first.substr(0, 12) != "_TECHMAP_DO_" && it.first.substr(0, 14) != "_TECHMAP_DONE_")
|
||||
log_error("Techmap yielded unknown config wire %s.\n", it.first.c_str());
|
||||
if (techmap_do_cache[tpl])
|
||||
for (auto &it2 : it.second)
|
||||
if (!it2.value.is_fully_const())
|
||||
log_error("Techmap yielded config wire %s with non-const value %s.\n", RTLIL::id2cstr(it2.wire->name), log_signal(it2.value));
|
||||
}
|
||||
}
|
||||
|
||||
TechmapWires twd = techmap_find_special_wires(tpl);
|
||||
for (auto &it : twd) {
|
||||
if (it.first != "_TECHMAP_FAIL_" && it.first.substr(0, 12) != "_TECHMAP_DO_" && it.first.substr(0, 14) != "_TECHMAP_DONE_")
|
||||
log_error("Techmap yielded unknown config wire %s.\n", it.first.c_str());
|
||||
if (techmap_do_cache[tpl])
|
||||
for (auto &it2 : it.second)
|
||||
if (!it2.value.is_fully_const())
|
||||
log_error("Techmap yielded config wire %s with non-const value %s.\n", RTLIL::id2cstr(it2.wire->name), log_signal(it2.value));
|
||||
if (techmap_do_cache.at(tpl) == false)
|
||||
continue;
|
||||
|
||||
if (log_continue) {
|
||||
log_header("Continuing TECHMAP pass.\n");
|
||||
log_continue = false;
|
||||
}
|
||||
|
||||
techmap_module_worker(design, module, cell, tpl, flatten_mode);
|
||||
did_something = true;
|
||||
cell = NULL;
|
||||
break;
|
||||
}
|
||||
|
||||
if (techmap_do_cache.at(tpl) == false)
|
||||
continue;
|
||||
|
||||
if (log_continue) {
|
||||
log_header("Continuing TECHMAP pass.\n");
|
||||
log_continue = false;
|
||||
}
|
||||
|
||||
techmap_module_worker(design, module, cell, tpl, flatten_mode);
|
||||
did_something = true;
|
||||
cell = NULL;
|
||||
break;
|
||||
handled_cells.insert(cell);
|
||||
}
|
||||
|
||||
handled_cells.insert(cell);
|
||||
}
|
||||
if (log_continue) {
|
||||
log_header("Continuing TECHMAP pass.\n");
|
||||
log_continue = false;
|
||||
}
|
||||
|
||||
if (log_continue) {
|
||||
log_header("Continuing TECHMAP pass.\n");
|
||||
log_continue = false;
|
||||
return did_something;
|
||||
}
|
||||
|
||||
return did_something;
|
||||
}
|
||||
};
|
||||
|
||||
struct TechmapPass : public Pass {
|
||||
TechmapPass() : Pass("techmap", "generic technology mapper") { }
|
||||
|
|
@ -469,7 +472,8 @@ struct TechmapPass : public Pass {
|
|||
}
|
||||
extra_args(args, argidx, design);
|
||||
|
||||
simplemap_get_mappers(simplemap_mappers);
|
||||
TechmapWorker worker;
|
||||
simplemap_get_mappers(worker.simplemap_mappers);
|
||||
|
||||
RTLIL::Design *map = new RTLIL::Design;
|
||||
if (map_files.empty()) {
|
||||
|
|
@ -509,17 +513,15 @@ struct TechmapPass : public Pass {
|
|||
while (did_something) {
|
||||
did_something = false;
|
||||
for (auto &mod_it : design->modules)
|
||||
if (techmap_module(design, mod_it.second, map, handled_cells, celltypeMap, false))
|
||||
if (worker.techmap_module(design, mod_it.second, map, handled_cells, celltypeMap, false))
|
||||
did_something = true;
|
||||
if (did_something)
|
||||
design->check();
|
||||
}
|
||||
|
||||
log("No more expansions possible.\n");
|
||||
techmap_cache.clear();
|
||||
techmap_do_cache.clear();
|
||||
simplemap_mappers.clear();
|
||||
delete map;
|
||||
|
||||
log_pop();
|
||||
}
|
||||
} TechmapPass;
|
||||
|
|
@ -544,6 +546,8 @@ struct FlattenPass : public Pass {
|
|||
|
||||
extra_args(args, 1, design);
|
||||
|
||||
TechmapWorker worker;
|
||||
|
||||
std::map<RTLIL::IdString, std::set<RTLIL::IdString>> celltypeMap;
|
||||
for (auto &it : design->modules)
|
||||
celltypeMap[it.first].insert(it.first);
|
||||
|
|
@ -559,11 +563,11 @@ struct FlattenPass : public Pass {
|
|||
while (did_something) {
|
||||
did_something = false;
|
||||
if (top_mod != NULL) {
|
||||
if (techmap_module(design, top_mod, design, handled_cells, celltypeMap, true))
|
||||
if (worker.techmap_module(design, top_mod, design, handled_cells, celltypeMap, true))
|
||||
did_something = true;
|
||||
} else {
|
||||
for (auto &mod_it : design->modules)
|
||||
if (techmap_module(design, mod_it.second, design, handled_cells, celltypeMap, true))
|
||||
if (worker.techmap_module(design, mod_it.second, design, handled_cells, celltypeMap, true))
|
||||
did_something = true;
|
||||
}
|
||||
}
|
||||
|
|
@ -582,8 +586,6 @@ struct FlattenPass : public Pass {
|
|||
design->modules.swap(new_modules);
|
||||
}
|
||||
|
||||
techmap_cache.clear();
|
||||
techmap_do_cache.clear();
|
||||
log_pop();
|
||||
}
|
||||
} FlattenPass;
|
||||
|
|
|
|||
Loading…
Reference in New Issue