mirror of https://github.com/YosysHQ/yosys.git
Add experimental adders pass
This commit is contained in:
Clifford Wolf
parent
d3b3dd8e88
commit
51cbec7f75
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@ -32,6 +32,7 @@ OBJS += passes/techmap/insbuf.o
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OBJS += passes/techmap/attrmvcp.o
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OBJS += passes/techmap/attrmap.o
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OBJS += passes/techmap/zinit.o
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OBJS += passes/techmap/adders.o
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endif
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GENFILES += passes/techmap/techmap.inc
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@ -0,0 +1,446 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/consteval.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct AddersConfig
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{
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bool enable_fa = false;
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bool enable_ha = false;
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bool enable_fs = false;
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bool enable_hs = false;
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};
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struct AddersWorker
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{
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const AddersConfig &config;
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Module *module;
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ConstEval ce;
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SigMap &sigmap;
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dict<SigBit, Cell*> driver;
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pool<SigBit> handled_bits;
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dict<tuple<SigBit, SigBit>, pool<SigBit>> part_xor;
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dict<tuple<SigBit, SigBit>, pool<SigBit>> part_and;
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dict<tuple<SigBit, SigBit>, pool<SigBit>> part_andnot;
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dict<tuple<SigBit, SigBit, SigBit>, pool<SigBit>> part_xor3;
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dict<tuple<SigBit, SigBit, SigBit>, pool<SigBit>> part_maj;
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dict<tuple<SigBit, SigBit, SigBit>, pool<SigBit>> part_majnot;
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AddersWorker(const AddersConfig &config, Module *module) :
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config(config), module(module), ce(module), sigmap(ce.assign_map)
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{
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for (auto cell : module->selected_cells())
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{
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if (cell->type.in( "$_BUF_", "$_NOT_", "$_AND_", "$_NAND_", "$_OR_", "$_NOR_",
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"$_XOR_", "$_XNOR_", "$_ANDNOT_", "$_ORNOT_", "$_MUX_",
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"$_AOI3_", "$_OAI3_", "$_AOI4_", "$_OAI4_"))
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{
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SigBit y = sigmap(SigBit(cell->getPort("\\Y")));
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log_assert(driver.count(y) == 0);
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driver[y] = cell;
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}
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}
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}
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void check_partition(SigBit root, pool<SigBit> &leaves)
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{
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if (GetSize(leaves) == 2)
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{
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leaves.sort();
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SigBit A = SigSpec(leaves)[0];
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SigBit B = SigSpec(leaves)[1];
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bool is_xor = true;
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bool is_and = true;
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bool is_andnot_a = true;
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bool is_andnot_b = true;
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for (int i = 0; i < 4; i++)
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{
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bool a_value = (i & 1) != 0;
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bool b_value = (i & 2) != 0;
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bool xor_value = a_value != b_value;
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bool and_value = a_value && b_value;
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bool andnot_a_value = !a_value && b_value;
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bool andnot_b_value = a_value && !b_value;
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ce.push();
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ce.set(A, a_value ? State::S1 : State::S0);
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ce.set(B, b_value ? State::S1 : State::S0);
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SigSpec sig = root;
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if (!ce.eval(sig))
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log_abort();
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if (sig != xor_value)
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is_xor = false;
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if (sig != and_value)
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is_and = false;
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if (sig != andnot_a_value)
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is_andnot_a = false;
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if (sig != andnot_b_value)
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is_andnot_b = false;
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ce.pop();
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}
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if (is_xor)
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part_xor[tuple<SigBit, SigBit>(A, B)].insert(root);
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if (is_and)
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part_and[tuple<SigBit, SigBit>(A, B)].insert(root);
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if (is_andnot_a)
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part_andnot[tuple<SigBit, SigBit>(B, A)].insert(root);
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if (is_andnot_b)
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part_andnot[tuple<SigBit, SigBit>(A, B)].insert(root);
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}
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if (GetSize(leaves) == 3)
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{
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leaves.sort();
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SigBit A = SigSpec(leaves)[0];
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SigBit B = SigSpec(leaves)[1];
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SigBit C = SigSpec(leaves)[2];
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bool is_xor3 = true;
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bool is_maj = true;
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bool is_maj_nota = true;
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bool is_maj_notb = true;
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bool is_maj_notc = true;
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for (int i = 0; i < 8; i++)
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{
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bool a_value = (i & 1) != 0;
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bool b_value = (i & 2) != 0;
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bool c_value = (i & 4) != 0;
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bool xor3_value = (a_value != b_value) != c_value;
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bool maj_value = (a_value && b_value) || (a_value && c_value) || (b_value && c_value);
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bool maj_nota_value = (!a_value && b_value) || (!a_value && c_value) || (b_value && c_value);
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bool maj_notb_value = (a_value && !b_value) || (a_value && c_value) || (!b_value && c_value);
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bool maj_notc_value = (a_value && b_value) || (a_value && !c_value) || (b_value && !c_value);
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ce.push();
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ce.set(A, a_value ? State::S1 : State::S0);
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ce.set(B, b_value ? State::S1 : State::S0);
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ce.set(C, c_value ? State::S1 : State::S0);
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SigSpec sig = root;
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if (!ce.eval(sig))
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log_abort();
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if (sig != xor3_value)
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is_xor3 = false;
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if (sig != maj_value)
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is_maj = false;
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if (sig != maj_nota_value)
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is_maj_nota = false;
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if (sig != maj_notb_value)
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is_maj_notb = false;
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if (sig != maj_notc_value)
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is_maj_notc = false;
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ce.pop();
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}
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if (is_xor3)
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part_xor3[tuple<SigBit, SigBit, SigBit>(A, B, C)].insert(root);
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if (is_maj)
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part_maj[tuple<SigBit, SigBit, SigBit>(A, B, C)].insert(root);
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if (is_maj_nota)
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part_majnot[tuple<SigBit, SigBit, SigBit>(B, C, A)].insert(root);
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if (is_maj_notb)
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part_majnot[tuple<SigBit, SigBit, SigBit>(A, C, B)].insert(root);
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if (is_maj_notc)
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part_majnot[tuple<SigBit, SigBit, SigBit>(A, B, C)].insert(root);
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}
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}
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void find_partitions(SigBit root, pool<SigBit> &leaves, pool<pool<SigBit>> &cache, int maxdepth, int maxbreadth)
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{
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if (cache.count(leaves))
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return;
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cache.insert(leaves);
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check_partition(root, leaves);
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if (maxdepth == 0)
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return;
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for (SigBit bit : leaves)
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{
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if (driver.count(bit) == 0)
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continue;
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Cell *cell = driver.at(bit);
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pool<SigBit> new_leaves = leaves;
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new_leaves.erase(bit);
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if (cell->hasPort("\\A")) new_leaves.insert(sigmap(SigBit(cell->getPort("\\A"))));
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if (cell->hasPort("\\B")) new_leaves.insert(sigmap(SigBit(cell->getPort("\\B"))));
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if (cell->hasPort("\\C")) new_leaves.insert(sigmap(SigBit(cell->getPort("\\C"))));
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if (cell->hasPort("\\D")) new_leaves.insert(sigmap(SigBit(cell->getPort("\\D"))));
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if (GetSize(new_leaves) > maxbreadth)
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continue;
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find_partitions(root, new_leaves, cache, maxdepth-1, maxbreadth);
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}
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}
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void make_fa(SigBit A, SigBit B, SigBit C, const pool<SigBit> &sum_out, const pool<SigBit> &carry_out)
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{
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if (!config.enable_fa)
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return;
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Wire *so = module->addWire(NEW_ID);
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Wire *co = module->addWire(NEW_ID);
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Cell *cell = module->addCell(NEW_ID, "$__fa");
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cell->setPort("\\A", A);
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cell->setPort("\\B", B);
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cell->setPort("\\C", C);
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cell->setPort("\\SO", so);
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cell->setPort("\\CO", co);
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log("New full adder %s in module %s: A=%s B=%s C=%s\n", log_id(cell), log_id(module), log_signal(A), log_signal(B), log_signal(C));
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for (auto bit : sum_out) {
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if (handled_bits.count(bit))
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continue;
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Cell *drv = driver.at(bit);
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drv->setPort("\\Y", module->addWire(NEW_ID));
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module->connect(bit, so);
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handled_bits.insert(bit);
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log(" sum out: %s\n", log_signal(bit));
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}
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for (auto bit : carry_out) {
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if (handled_bits.count(bit))
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continue;
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Cell *drv = driver.at(bit);
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drv->setPort("\\Y", module->addWire(NEW_ID));
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module->connect(bit, co);
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handled_bits.insert(bit);
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log(" carry out: %s\n", log_signal(bit));
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}
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}
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void make_ha(SigBit A, SigBit B, const pool<SigBit> &sum_out, const pool<SigBit> &carry_out)
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{
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if (!config.enable_ha)
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return;
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Wire *so = module->addWire(NEW_ID);
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Wire *co = module->addWire(NEW_ID);
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Cell *cell = module->addCell(NEW_ID, "$__ha");
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cell->setPort("\\A", A);
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cell->setPort("\\B", B);
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cell->setPort("\\SO", so);
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cell->setPort("\\CO", co);
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log("New half adder %s in module %s: A=%s B=%s\n", log_id(cell), log_id(module), log_signal(A), log_signal(B));
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for (auto bit : sum_out) {
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if (handled_bits.count(bit))
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continue;
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Cell *drv = driver.at(bit);
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drv->setPort("\\Y", module->addWire(NEW_ID));
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module->connect(bit, so);
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handled_bits.insert(bit);
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log(" sum out: %s\n", log_signal(bit));
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}
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for (auto bit : carry_out) {
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if (handled_bits.count(bit))
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continue;
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Cell *drv = driver.at(bit);
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drv->setPort("\\Y", module->addWire(NEW_ID));
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module->connect(bit, co);
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handled_bits.insert(bit);
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log(" carry out: %s\n", log_signal(bit));
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}
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}
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void make_hs(SigBit A, SigBit B, const pool<SigBit> &sum_out, const pool<SigBit> &carry_out)
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{
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if (!config.enable_hs)
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return;
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Wire *so = module->addWire(NEW_ID);
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Wire *co = module->addWire(NEW_ID);
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Cell *cell = module->addCell(NEW_ID, "$__hs");
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cell->setPort("\\A", A);
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cell->setPort("\\B", B);
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cell->setPort("\\SO", so);
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cell->setPort("\\CO", co);
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log("New half subtractor %s in module %s: A=%s B=%s\n", log_id(cell), log_id(module), log_signal(A), log_signal(B));
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for (auto bit : sum_out) {
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if (handled_bits.count(bit))
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continue;
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Cell *drv = driver.at(bit);
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drv->setPort("\\Y", module->addWire(NEW_ID));
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module->connect(bit, so);
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handled_bits.insert(bit);
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log(" sum out: %s\n", log_signal(bit));
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}
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for (auto bit : carry_out) {
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if (handled_bits.count(bit))
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continue;
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Cell *drv = driver.at(bit);
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drv->setPort("\\Y", module->addWire(NEW_ID));
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module->connect(bit, co);
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handled_bits.insert(bit);
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log(" carry out: %s\n", log_signal(bit));
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}
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}
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void run()
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{
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for (auto it : driver)
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{
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SigBit root = it.first;
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pool<SigBit> leaves = { root };
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pool<pool<SigBit>> cache;
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find_partitions(root, leaves, cache, 5, 10);
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}
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for (auto &it : part_xor3)
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{
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SigBit A = get<0>(it.first);
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SigBit B = get<1>(it.first);
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SigBit C = get<2>(it.first);
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// FIXME: Add support for full subtractors
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if (part_maj.count(tuple<SigBit, SigBit, SigBit>(A, B, C)))
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make_fa(A, B, C, it.second, part_maj.at(tuple<SigBit, SigBit, SigBit>(A, B, C)));
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}
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for (auto &it : part_xor)
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{
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SigBit A = get<0>(it.first);
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SigBit B = get<1>(it.first);
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if (part_andnot.count(tuple<SigBit, SigBit>(A, B)))
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make_hs(A, B, it.second, part_andnot.at(tuple<SigBit, SigBit>(A, B)));
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if (part_andnot.count(tuple<SigBit, SigBit>(B, A)))
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make_hs(B, A, it.second, part_andnot.at(tuple<SigBit, SigBit>(B, A)));
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if (part_and.count(tuple<SigBit, SigBit>(A, B)))
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make_ha(A, B, it.second, part_and.at(tuple<SigBit, SigBit>(A, B)));
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}
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}
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};
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struct AddersPass : public Pass {
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AddersPass() : Pass("adders", "find and extract full/half adders/subtractors") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" adders [options] [selection]\n");
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log("\n");
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log("This pass extracts full/half adders/subtractors from a gate-level design.\n");
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log("\n");
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log(" -fa, -ha, -fs, -hs\n");
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log(" Enable cell types (f=full, h=half, a=adder, s=subtractor)\n");
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log(" All types are enabled if none of this options is used\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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AddersConfig config;
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log_header(design, "Executing ADDERS pass (find and extract full/half adders/subtractors).\n");
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log_push();
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-fa") {
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config.enable_fa = true;
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continue;
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}
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if (args[argidx] == "-ha") {
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config.enable_ha = true;
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continue;
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}
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if (args[argidx] == "-fs") {
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config.enable_fs = true;
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continue;
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}
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if (args[argidx] == "-hs") {
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config.enable_hs = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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if (!config.enable_fa && !config.enable_ha && !config.enable_fs && !config.enable_hs) {
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config.enable_fa = true;
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config.enable_ha = true;
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config.enable_fs = true;
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config.enable_hs = true;
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}
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for (auto module : design->selected_modules())
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{
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AddersWorker worker(config, module);
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worker.run();
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}
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log_pop();
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}
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} AddersPass;
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PRIVATE_NAMESPACE_END
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