mirror of https://github.com/YosysHQ/yosys.git
Bugfix in $memrd sharing
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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@ -710,8 +710,12 @@ struct ShareWorker
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RTLIL::Cell *supercell = module->addCell(NEW_ID, c1);
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RTLIL::SigSpec addr1 = c1->getPort("\\ADDR");
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RTLIL::SigSpec addr2 = c2->getPort("\\ADDR");
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if (addr1 != addr2)
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supercell->setPort("\\ADDR", module->Mux(NEW_ID, addr2, addr1, act));
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if (GetSize(addr1) < GetSize(addr2))
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addr1.extend_u0(GetSize(addr2));
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else
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addr2.extend_u0(GetSize(addr1));
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supercell->setPort("\\ADDR", addr1 != addr2 ? module->Mux(NEW_ID, addr2, addr1, act) : addr1);
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supercell->parameters["\\ABITS"] = RTLIL::Const(GetSize(addr1));
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supercell_aux.insert(module->addPos(NEW_ID, supercell->getPort("\\DATA"), c2->getPort("\\DATA")));
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supercell_aux.insert(supercell);
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return supercell;
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