mirror of https://github.com/YosysHQ/yosys.git
Added SAT generator and simple sat_solve command
This commit is contained in:
Clifford Wolf
parent
3371563f2f
commit
46fbe9d262
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@ -186,12 +186,11 @@ AstNode *VERILOG_FRONTEND::const2ast(std::string code, char case_type)
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my_strtobin(data, endptr+2, len_in_bits, 16, case_type);
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break;
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default:
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goto error;
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return NULL;
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}
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return AstNode::mkconst_bits(data, is_signed);
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}
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error:
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log_error("Value conversion failed: `%s'\n", code.c_str());
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return NULL;
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}
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@ -912,6 +912,8 @@ basic_expr:
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} |
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TOK_CONST {
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$$ = const2ast(*$1, case_type_stack.size() == 0 ? 0 : case_type_stack.back());
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if ($$ == NULL)
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log_error("Value conversion failed: `%s'\n", $1->c_str());
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delete $1;
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} |
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TOK_STRING {
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@ -0,0 +1,137 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef SATGEN_H
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#define SATGEN_H
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#include "kernel/rtlil.h"
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#include "kernel/sigtools.h"
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#include "kernel/celltypes.h"
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#ifdef YOSYS_ENABLE_MINISAT
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# include "libs/ezsat/ezminisat.h"
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typedef ezMiniSAT ezDefaultSAT;
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#else
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# include "libs/ezsat/ezsat.h"
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typedef ezSAT ezDefaultSAT;
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#endif
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struct SatGen
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{
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ezSAT *ez;
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RTLIL::Design *design;
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SigMap *sigmap;
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std::string prefix;
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SatGen(ezSAT *ez, RTLIL::Design *design, SigMap *sigmap, std::string prefix = std::string()) :
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ez(ez), design(design), sigmap(sigmap), prefix(prefix)
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{
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}
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void setContext(RTLIL::Design *design, SigMap *sigmap, std::string prefix = std::string())
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{
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this->design = design;
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this->sigmap = sigmap;
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this->prefix = prefix;
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}
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virtual ~SatGen()
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{
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}
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virtual std::vector<int> importSigSpec(RTLIL::SigSpec &sig)
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{
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RTLIL::SigSpec s = sig;
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sigmap->apply(s);
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s.expand();
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std::vector<int> vec;
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vec.reserve(s.chunks.size());
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for (auto &c : s.chunks)
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if (c.wire == NULL)
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vec.push_back(c.data.as_bool() ? ez->TRUE : ez->FALSE);
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else
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vec.push_back(ez->literal(prefix + stringf(c.wire->width == 1 ?
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"%s" : "%s [%d]", RTLIL::id2cstr(c.wire->name), c.offset)));
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return vec;
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}
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// ** cell types to be done: **
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// cell_types.insert("$pos");
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// cell_types.insert("$neg");
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// cell_types.insert("$xnor");
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// cell_types.insert("$reduce_and");
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// cell_types.insert("$reduce_or");
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// cell_types.insert("$reduce_xor");
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// cell_types.insert("$reduce_xnor");
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// cell_types.insert("$reduce_bool");
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// cell_types.insert("$shl");
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// cell_types.insert("$shr");
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// cell_types.insert("$sshl");
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// cell_types.insert("$sshr");
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// cell_types.insert("$lt");
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// cell_types.insert("$le");
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// cell_types.insert("$eq");
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// cell_types.insert("$ne");
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// cell_types.insert("$ge");
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// cell_types.insert("$gt");
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// cell_types.insert("$add");
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// cell_types.insert("$sub");
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// cell_types.insert("$mul");
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// cell_types.insert("$div");
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// cell_types.insert("$mod");
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// cell_types.insert("$pow");
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// cell_types.insert("$logic_not");
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// cell_types.insert("$logic_and");
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// cell_types.insert("$logic_or");
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// cell_types.insert("$pmux");
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// cell_types.insert("$safe_pmux");
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virtual void importCell(RTLIL::Cell *cell)
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{
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if (cell->type == "$_AND_" || cell->type == "$_OR_" || cell->type == "$_XOR_" ||
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cell->type == "$and" || cell->type == "$or" || cell->type == "$xor") {
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std::vector<int> a = importSigSpec(cell->connections.at("\\A"));
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std::vector<int> b = importSigSpec(cell->connections.at("\\B"));
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std::vector<int> y = importSigSpec(cell->connections.at("\\Y"));
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if (cell->type == "$and" || cell->type == "$_AND_")
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ez->assume(ez->vec_eq(ez->vec_and(a, b), y));
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if (cell->type == "$or" || cell->type == "$_OR_")
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ez->assume(ez->vec_eq(ez->vec_or(a, b), y));
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if (cell->type == "$xor" || cell->type == "$_XOR")
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ez->assume(ez->vec_eq(ez->vec_xor(a, b), y));
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} else
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if (cell->type == "$_INV_" || cell->type == "$not") {
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std::vector<int> a = importSigSpec(cell->connections.at("\\A"));
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std::vector<int> y = importSigSpec(cell->connections.at("\\Y"));
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ez->assume(ez->vec_eq(ez->vec_not(a), y));
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} else
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if (cell->type == "$_MUX_" || cell->type == "$mux") {
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std::vector<int> a = importSigSpec(cell->connections.at("\\A"));
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std::vector<int> b = importSigSpec(cell->connections.at("\\B"));
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std::vector<int> s = importSigSpec(cell->connections.at("\\S"));
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std::vector<int> y = importSigSpec(cell->connections.at("\\Y"));
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ez->assume(ez->vec_eq(ez->vec_ite(s, b, a), y));
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} else
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log_error("Can't handle cell type %s in SAT generator yet.\n", RTLIL::id2cstr(cell->type));
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}
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};
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#endif
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@ -0,0 +1,3 @@
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OBJS += passes/sat/sat_solve.o
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@ -0,0 +1,12 @@
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module example(a, y);
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input [15:0] a;
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output y;
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wire gt = a > 12345;
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wire lt = a < 12345;
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assign y = !gt && !lt;
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endmodule
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@ -0,0 +1,3 @@
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read_verilog example.v
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techmap; opt
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sat_solve -show a -set y 1'b1
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@ -0,0 +1,241 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/celltypes.h"
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#include "kernel/sigtools.h"
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#include "kernel/log.h"
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#include "kernel/satgen.h"
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#include "frontends/verilog/verilog_frontend.h"
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#include <stdlib.h>
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#include <stdio.h>
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#include <algorithm>
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static void split(std::vector<std::string> &tokens, const std::string &text, char sep)
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{
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size_t start = 0, end = 0;
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while ((end = text.find(sep, start)) != std::string::npos) {
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tokens.push_back(text.substr(start, end - start));
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start = end + 1;
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}
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tokens.push_back(text.substr(start));
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}
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bool parse_sigstr(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
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{
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std::vector<std::string> tokens;
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split(tokens, str, ',');
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sig = RTLIL::SigSpec();
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for (auto &tok : tokens)
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{
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std::string netname = tok;
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std::string indices;
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if (netname.size() == 0)
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continue;
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if ('0' <= netname[0] && netname[0] <= '9') {
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AST::AstNode *ast = VERILOG_FRONTEND::const2ast(netname);
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if (ast == NULL)
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return false;
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sig.append(RTLIL::Const(ast->bits));
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delete ast;
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continue;
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}
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if (netname[0] != '$' && netname[0] != '\\')
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netname = "\\" + netname;
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if (module->wires.count(netname) == 0) {
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size_t indices_pos = netname.size()-1;
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if (indices_pos > 2 && netname[indices_pos] == ']')
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{
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indices_pos--;
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while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
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if (indices_pos > 0 && netname[indices_pos] == ':') {
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indices_pos--;
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while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
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}
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if (indices_pos > 0 && netname[indices_pos] == '[') {
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indices = netname.substr(indices_pos);
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netname = netname.substr(0, indices_pos);
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}
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}
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}
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if (module->wires.count(netname) == 0)
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return false;
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RTLIL::Wire *wire = module->wires.at(netname);
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if (!indices.empty()) {
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std::vector<std::string> index_tokens;
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split(index_tokens, indices.substr(1, indices.size()-2), ':');
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if (index_tokens.size() == 1)
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sig.append(RTLIL::SigSpec(wire, 1, atoi(index_tokens.at(0).c_str())));
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else {
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int a = atoi(index_tokens.at(0).c_str());
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int b = atoi(index_tokens.at(1).c_str());
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if (a > b) {
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int tmp = a;
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a = b, b = tmp;
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}
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sig.append(RTLIL::SigSpec(wire, b-a+1, a));
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}
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} else
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sig.append(wire);
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}
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return true;
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}
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struct SatSolvePass : public Pass {
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SatSolvePass() : Pass("sat_solve", "solve a SAT problem in the circuit") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" sat_solve [options] [selection]\n");
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log("\n");
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log("This command solves a SAT problem defined over the currently selected circuit\n");
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log("and additional constraints passed as parameters.\n");
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log("\n");
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log(" -set <signal> <value>\n");
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log(" set the specified signal to the specified value.\n");
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log("\n");
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log(" -show <signal>n");
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log(" show the model for the specified signal. if no -show option\n");
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log(" is passed then all selected signals will be shown.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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std::vector<std::pair<std::string, std::string>> sets;
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std::vector<std::string> shows;
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log_header("Executing SAT_SOLVE pass (detecting logic loops).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-set" && argidx+2 < args.size()) {
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std::string lhs = args[++argidx].c_str();
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std::string rhs = args[++argidx].c_str();
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sets.push_back(std::pair<std::string, std::string>(lhs, rhs));
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continue;
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}
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if (args[argidx] == "-show" && argidx+1 < args.size()) {
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shows.push_back(args[++argidx]);
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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RTLIL::Module *module = NULL;
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for (auto &mod_it : design->modules)
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if (design->selected(mod_it.second)) {
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if (module)
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log_cmd_error("Only one module must be selected for the SAT_SOLVE pass! (selected: %s and %s)\n",
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RTLIL::id2cstr(module->name), RTLIL::id2cstr(mod_it.first));
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module = mod_it.second;
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}
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if (module == NULL)
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log_cmd_error("Can't perform SAT_SOLVE on an empty selection!\n");
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ezDefaultSAT ez;
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SigMap sigmap(module);
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SatGen satgen(&ez, design, &sigmap);
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for (auto &s : sets)
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{
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RTLIL::SigSpec lhs, rhs;
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if (!parse_sigstr(lhs, module, s.first))
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log_cmd_error("Failed to parse lhs set expression `%s'.\n", s.first.c_str());
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if (!parse_sigstr(rhs, module, s.second))
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log_cmd_error("Failed to parse rhs set expression `%s'.\n", s.second.c_str());
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if (lhs.width != rhs.width)
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log_cmd_error("Set expression with different lhs and rhs sizes: %s (%s, %d bits) vs. %s (%s, %d bits)\n",
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s.first.c_str(), log_signal(lhs), lhs.width, s.second.c_str(), log_signal(rhs), rhs.width);
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log("Import constraint: %s = %s\n", log_signal(lhs), log_signal(rhs));
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std::vector<int> lhs_vec = satgen.importSigSpec(lhs);
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std::vector<int> rhs_vec = satgen.importSigSpec(rhs);
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ez.assume(ez.vec_eq(lhs_vec, rhs_vec));
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}
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int import_cell_counter = 0;
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for (auto &c : module->cells)
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if (design->selected(module, c.second)) {
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// log("Import cell: %s\n", RTLIL::id2cstr(c.first));
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satgen.importCell(c.second);
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import_cell_counter++;
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}
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log("Imported %d cells.\n", import_cell_counter);
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std::vector<int> modelExpressions;
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std::vector<bool> modelValues;
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std::vector<std::string> modelNames;
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int maxModelName = 0;
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if (shows.size() == 0) {
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for (auto &w : module->wires)
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if (design->selected(module, w.second)) {
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RTLIL::Wire *wire = w.second;
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for (int i = 0; i < wire->width; i++) {
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RTLIL::SigSpec sig = RTLIL::SigSpec(wire, 1, i);
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std::vector<int> vec = satgen.importSigSpec(sig);
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log_assert(vec.size() == 1);
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modelExpressions.push_back(vec[0]);
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modelNames.push_back(log_signal(sig));
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maxModelName = std::max(maxModelName, int(modelNames.back().size()));
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}
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}
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} else {
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for (auto &s : shows) {
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RTLIL::SigSpec sig;
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if (!parse_sigstr(sig, module, s))
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log_cmd_error("Failed to parse show expression `%s'.\n", s.c_str());
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sig.expand();
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log("Import show expression: %s\n", log_signal(sig));
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for (auto &c : sig.chunks) {
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RTLIL::SigSpec chunksig = c;
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std::vector<int> vec = satgen.importSigSpec(chunksig);
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log_assert(vec.size() == 1);
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modelExpressions.push_back(vec[0]);
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modelNames.push_back(log_signal(chunksig));
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maxModelName = std::max(maxModelName, int(modelNames.back().size()));
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}
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}
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}
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log("Solving problem with %d variables and %d clauses..\n", ez.numCnfVariables(), int(ez.cnf().size()));
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if (ez.solve(modelExpressions, modelValues))
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{
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log("SAT solving finished - model found:\n");
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for (size_t i = 0; i < modelNames.size(); i++)
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log(" %-*s %s\n", maxModelName, modelNames.at(i).c_str(), modelValues.at(i) ? "1" : "0");
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}
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else
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log("SAT solving finished - no model found.\n");
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}
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} SatSolvePass;
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