mirror of https://github.com/YosysHQ/yosys.git
WIP for ABC with aiger
This commit is contained in:
Eddie Hung
parent
0124512f28
commit
b3341b4abb
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@ -31,7 +31,7 @@
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#define ABC_COMMAND_LIB "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put"
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#define ABC_COMMAND_CTR "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put; buffer; upsize {D}; dnsize {D}; stime -p"
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#define ABC_COMMAND_LUT "strash; ifraig; scorr; dc2; dretime; strash; dch -f; if; mfs2"
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#define ABC_COMMAND_LUT "&st; &fraig; &scorr; &dc2; &retime; &dch -f; &if;"/*" &mfs"*/
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#define ABC_COMMAND_SOP "strash; ifraig; scorr; dc2; dretime; strash; dch -f; cover {I} {P}"
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#define ABC_COMMAND_DFL "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put"
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@ -58,7 +58,7 @@
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# include <dirent.h>
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#endif
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#include "frontends/blif/blifparse.h"
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#include "frontends/aiger/aigerparse.h"
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#ifdef YOSYS_LINK_ABC
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extern "C" int Abc_RealMain(int argc, char *argv[]);
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@ -672,10 +672,10 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
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if (!cleanup)
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tempdir_name[0] = tempdir_name[4] = '_';
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tempdir_name = make_temp_dir(tempdir_name);
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log_header(design, "Extracting gate netlist of module `%s' to `%s/input.blif'..\n",
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log_header(design, "Extracting gate netlist of module `%s' to `%s/input.xaig'..\n",
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module->name.c_str(), replace_tempdir(tempdir_name, tempdir_name, show_tempdir).c_str());
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std::string abc_script = stringf("read_blif %s/input.blif; ", tempdir_name.c_str());
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std::string abc_script = stringf("&read %s/input.xaig; ", tempdir_name.c_str());
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if (!liberty_file.empty()) {
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abc_script += stringf("read_lib -w %s; ", liberty_file.c_str());
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@ -704,8 +704,8 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
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if (this_cost != lut_costs.front())
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all_luts_cost_same = false;
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abc_script += fast_mode ? ABC_FAST_COMMAND_LUT : ABC_COMMAND_LUT;
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if (all_luts_cost_same && !fast_mode)
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abc_script += "; lutpack {S}";
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//if (all_luts_cost_same && !fast_mode)
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// abc_script += "; lutpack {S}";
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} else if (!liberty_file.empty())
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abc_script += constr_file.empty() ? (fast_mode ? ABC_FAST_COMMAND_LIB : ABC_COMMAND_LIB) : (fast_mode ? ABC_FAST_COMMAND_CTR : ABC_COMMAND_CTR);
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else if (sop_mode)
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@ -729,7 +729,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
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for (size_t pos = abc_script.find("{S}"); pos != std::string::npos; pos = abc_script.find("{S}", pos))
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abc_script = abc_script.substr(0, pos) + lutin_shared + abc_script.substr(pos+3);
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abc_script += stringf("; write_blif %s/output.blif", tempdir_name.c_str());
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abc_script += stringf("; &write -v %s/output.xaig", tempdir_name.c_str());
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abc_script = add_echos_to_abc_cmd(abc_script);
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for (size_t i = 0; i+1 < abc_script.size(); i++)
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@ -772,129 +772,15 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
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handle_loops();
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std::string buffer = stringf("%s/input.blif", tempdir_name.c_str());
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f = fopen(buffer.c_str(), "wt");
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if (f == NULL)
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log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno));
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Pass::call(design, stringf("aigmap; write_xaiger %s/input.xaig", tempdir_name.c_str()));
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fprintf(f, ".model netlist\n");
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int count_input = 0;
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fprintf(f, ".inputs");
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for (auto &si : signal_list) {
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if (!si.is_port || si.type != G(NONE))
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continue;
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fprintf(f, " n%d", si.id);
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pi_map[count_input++] = log_signal(si.bit);
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}
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if (count_input == 0)
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fprintf(f, " dummy_input\n");
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fprintf(f, "\n");
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int count_output = 0;
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fprintf(f, ".outputs");
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for (auto &si : signal_list) {
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if (!si.is_port || si.type == G(NONE))
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continue;
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fprintf(f, " n%d", si.id);
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po_map[count_output++] = log_signal(si.bit);
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}
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fprintf(f, "\n");
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for (auto &si : signal_list)
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fprintf(f, "# n%-5d %s\n", si.id, log_signal(si.bit));
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for (auto &si : signal_list) {
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if (si.bit.wire == NULL) {
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fprintf(f, ".names n%d\n", si.id);
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if (si.bit == RTLIL::State::S1)
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fprintf(f, "1\n");
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}
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}
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int count_gates = 0;
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for (auto &si : signal_list) {
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if (si.type == G(BUF)) {
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fprintf(f, ".names n%d n%d\n", si.in1, si.id);
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fprintf(f, "1 1\n");
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} else if (si.type == G(NOT)) {
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fprintf(f, ".names n%d n%d\n", si.in1, si.id);
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fprintf(f, "0 1\n");
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} else if (si.type == G(AND)) {
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fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id);
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fprintf(f, "11 1\n");
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} else if (si.type == G(NAND)) {
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fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id);
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fprintf(f, "0- 1\n");
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fprintf(f, "-0 1\n");
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} else if (si.type == G(OR)) {
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fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id);
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fprintf(f, "-1 1\n");
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fprintf(f, "1- 1\n");
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} else if (si.type == G(NOR)) {
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fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id);
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fprintf(f, "00 1\n");
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} else if (si.type == G(XOR)) {
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fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id);
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fprintf(f, "01 1\n");
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fprintf(f, "10 1\n");
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} else if (si.type == G(XNOR)) {
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fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id);
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fprintf(f, "00 1\n");
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fprintf(f, "11 1\n");
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} else if (si.type == G(ANDNOT)) {
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fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id);
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fprintf(f, "10 1\n");
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} else if (si.type == G(ORNOT)) {
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fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id);
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fprintf(f, "1- 1\n");
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fprintf(f, "-0 1\n");
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} else if (si.type == G(MUX)) {
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fprintf(f, ".names n%d n%d n%d n%d\n", si.in1, si.in2, si.in3, si.id);
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fprintf(f, "1-0 1\n");
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fprintf(f, "-11 1\n");
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} else if (si.type == G(AOI3)) {
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fprintf(f, ".names n%d n%d n%d n%d\n", si.in1, si.in2, si.in3, si.id);
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fprintf(f, "-00 1\n");
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fprintf(f, "0-0 1\n");
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} else if (si.type == G(OAI3)) {
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fprintf(f, ".names n%d n%d n%d n%d\n", si.in1, si.in2, si.in3, si.id);
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fprintf(f, "00- 1\n");
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fprintf(f, "--0 1\n");
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} else if (si.type == G(AOI4)) {
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fprintf(f, ".names n%d n%d n%d n%d n%d\n", si.in1, si.in2, si.in3, si.in4, si.id);
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fprintf(f, "-0-0 1\n");
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fprintf(f, "-00- 1\n");
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fprintf(f, "0--0 1\n");
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fprintf(f, "0-0- 1\n");
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} else if (si.type == G(OAI4)) {
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fprintf(f, ".names n%d n%d n%d n%d n%d\n", si.in1, si.in2, si.in3, si.in4, si.id);
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fprintf(f, "00-- 1\n");
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fprintf(f, "--00 1\n");
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} else if (si.type == G(FF)) {
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if (si.init == State::S0 || si.init == State::S1) {
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fprintf(f, ".latch n%d n%d %d\n", si.in1, si.id, si.init == State::S1 ? 1 : 0);
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recover_init = true;
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} else
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fprintf(f, ".latch n%d n%d 2\n", si.in1, si.id);
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} else if (si.type != G(NONE))
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log_abort();
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if (si.type != G(NONE))
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count_gates++;
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}
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fprintf(f, ".end\n");
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fclose(f);
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log("Extracted %d gates and %d wires to a netlist network with %d inputs and %d outputs.\n",
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count_gates, GetSize(signal_list), count_input, count_output);
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log_push();
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if (count_output > 0)
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//if (count_output > 0)
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{
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log_header(design, "Executing ABC.\n");
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buffer = stringf("%s/stdcells.genlib", tempdir_name.c_str());
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std::string buffer = stringf("%s/stdcells.genlib", tempdir_name.c_str());
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f = fopen(buffer.c_str(), "wt");
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if (f == NULL)
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log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno));
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@ -970,7 +856,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
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if (ret != 0)
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log_error("ABC: execution of command \"%s\" failed: return code %d.\n", buffer.c_str(), ret);
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buffer = stringf("%s/%s", tempdir_name.c_str(), "output.blif");
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buffer = stringf("%s/%s", tempdir_name.c_str(), "output.xaig");
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std::ifstream ifs;
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ifs.open(buffer);
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if (ifs.fail())
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@ -978,7 +864,9 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
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bool builtin_lib = liberty_file.empty();
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RTLIL::Design *mapped_design = new RTLIL::Design;
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parse_blif(mapped_design, ifs, builtin_lib ? "\\DFF" : "\\_dff_", false, sop_mode);
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//parse_blif(mapped_design, ifs, builtin_lib ? "\\DFF" : "\\_dff_", false, sop_mode);
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AigerReader reader(mapped_design, ifs, "\\netlist", "\\clk");
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reader.parse_aiger();
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ifs.close();
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@ -1232,10 +1120,10 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
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delete mapped_design;
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}
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else
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{
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log("Don't call ABC as there is nothing to map.\n");
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}
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//else
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//{
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// log("Don't call ABC as there is nothing to map.\n");
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//}
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if (cleanup)
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{
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@ -1441,6 +1329,7 @@ struct Abc9Pass : public Pass {
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std::string delay_target, sop_inputs, sop_products, lutin_shared = "-S 1";
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bool fast_mode = false, dff_mode = false, keepff = false, cleanup = true;
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bool show_tempdir = false, sop_mode = false;
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show_tempdir = true; cleanup = false;
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vector<int> lut_costs;
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markgroups = false;
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