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Signed extension

This commit is contained in:
Eddie Hung 2019-07-16 15:54:07 -07:00
parent 6390c535ba
commit 3f677fb0db
2 changed files with 6 additions and 6 deletions
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4
passes/pmgen/xilinx_dsp.cc
View File

@ -50,7 +50,7 @@ void pack_xilinx_dsp(xilinx_dsp_pm &pm)
if (st.ffA) {
SigSpec D = st.ffA->getPort("\\D");
cell->setPort("\\A", D.extend_u0(30));
cell->setPort("\\A", D.extend_u0(30, true));
cell->setParam("\\AREG", State::S1);
if (st.ffA->type == "$dff")
cell->setPort("\\CEA2", State::S1);
@ -60,7 +60,7 @@ void pack_xilinx_dsp(xilinx_dsp_pm &pm)
}
if (st.ffB) {
SigSpec D = st.ffB->getPort("\\D");
cell->setPort("\\B", D.extend_u0(18));
cell->setPort("\\B", D.extend_u0(18, true));
cell->setParam("\\BREG", State::S1);
if (st.ffB->type == "$dff")
cell->setPort("\\CEB2", State::S1);

8
passes/pmgen/xilinx_dsp.pmg
View File

@ -9,10 +9,10 @@ endmatch
match ffA
select ffA->type.in($dff, $dffe)
select param(ffA, \CLK_POLARITY).as_bool()
// select nusers(port(ffA, \Q)) == 2
index <SigSpec> port(ffA, \Q).extend_u0(30) === port(dsp, \A)
index <SigSpec> port(ffA, \Q).extend_u0(25, true) === port(dsp, \A).extract(0, 25)
// DSP48E1 does not support clock inversion
index <Const> param(ffA, \CLK_POLARITY).as_bool() === true
optional
endmatch
@ -23,9 +23,9 @@ endcode
match ffB
select ffB->type.in($dff, $dffe)
select param(ffB, \CLK_POLARITY).as_bool()
// select nusers(port(ffB, \Q)) == 2
index <SigSpec> port(ffB, \Q).extend_u0(18) === port(dsp, \B)
index <Const> param(ffB, \CLK_POLARITY).as_bool() === true
index <SigSpec> port(ffB, \Q).extend_u0(18, true) === port(dsp, \B)
optional
endmatch