mirror of https://github.com/YosysHQ/yosys.git
duplicate -> clone
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@ -761,11 +761,11 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
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auto jt = bit2sinks.find(a_bit);
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if (jt == bit2sinks.end())
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goto duplicate_lut;
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goto clone_lut;
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for (auto sink_cell : jt->second)
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if (sink_cell->type != "$lut")
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goto duplicate_lut;
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goto clone_lut;
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// Push downstream LUTs past inverter
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for (auto sink_cell : jt->second) {
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@ -787,7 +787,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
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sink_cell->setParam("\\LUT", mask);
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}
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duplicate_lut:
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clone_lut:
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driver_mask = driver_lut->getParam("\\LUT");
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for (auto &b : driver_mask.bits) {
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if (b == RTLIL::State::S0) b = RTLIL::State::S1;
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