mirror of https://github.com/YosysHQ/yosys.git
Added "test_abcloop" command
This commit is contained in:
Clifford Wolf
parent
00964f2f61
commit
a7758ef953
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@ -1,4 +1,5 @@
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OBJS += passes/tests/test_autotb.o
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OBJS += passes/tests/test_cell.o
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OBJS += passes/tests/test_abcloop.o
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@ -0,0 +1,285 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2014 Clifford Wolf <clifford@clifford.at>
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* Copyright (C) 2014 Johann Glaser <Johann.Glaser@gmx.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/satgen.h"
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static uint32_t xorshift32_state = 123456789;
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static uint32_t xorshift32(uint32_t limit) {
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xorshift32_state ^= xorshift32_state << 13;
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xorshift32_state ^= xorshift32_state >> 17;
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xorshift32_state ^= xorshift32_state << 5;
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return xorshift32_state % limit;
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}
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static RTLIL::Wire *getw(std::vector<RTLIL::Wire*> &wires, RTLIL::Wire *w)
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{
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while (1) {
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int idx = xorshift32(SIZE(wires));
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if (wires[idx] != w && !wires[idx]->port_output)
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return wires[idx];
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}
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}
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static void test_abcloop()
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{
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log("Rng seed value: %u\n", int(xorshift32_state));
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RTLIL::Design *design = new RTLIL::Design;
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RTLIL::Module *module = nullptr;
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RTLIL::SigSpec in_sig, out_sig;
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bool truthtab[16][4];
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int create_cycles = 0;
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while (1)
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{
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module = design->addModule("\\uut");
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create_cycles++;
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in_sig = {};
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out_sig = {};
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std::vector<RTLIL::Wire*> wires;
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for (int i = 0; i < 4; i++) {
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RTLIL::Wire *w = module->addWire(stringf("\\i%d", i));
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w->port_input = true;
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wires.push_back(w);
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in_sig.append(w);
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}
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for (int i = 0; i < 4; i++) {
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RTLIL::Wire *w = module->addWire(stringf("\\o%d", i));
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w->port_output = true;
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wires.push_back(w);
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out_sig.append(w);
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}
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for (int i = 0; i < 16; i++) {
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RTLIL::Wire *w = module->addWire(stringf("\\t%d", i));
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wires.push_back(w);
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}
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for (auto w : wires)
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if (!w->port_input)
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switch (xorshift32(12))
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{
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case 0:
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module->addNotGate(w->name.str() + "g", getw(wires, w), w);
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break;
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case 1:
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module->addAndGate(w->name.str() + "g", getw(wires, w), getw(wires, w), w);
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break;
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case 2:
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module->addNandGate(w->name.str() + "g", getw(wires, w), getw(wires, w), w);
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break;
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case 3:
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module->addOrGate(w->name.str() + "g", getw(wires, w), getw(wires, w), w);
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break;
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case 4:
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module->addNorGate(w->name.str() + "g", getw(wires, w), getw(wires, w), w);
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break;
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case 5:
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module->addXorGate(w->name.str() + "g", getw(wires, w), getw(wires, w), w);
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break;
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case 6:
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module->addXnorGate(w->name.str() + "g", getw(wires, w), getw(wires, w), w);
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break;
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case 7:
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module->addMuxGate(w->name.str() + "g", getw(wires, w), getw(wires, w), getw(wires, w), w);
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break;
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case 8:
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module->addAoi3Gate(w->name.str() + "g", getw(wires, w), getw(wires, w), getw(wires, w), w);
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break;
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case 9:
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module->addOai3Gate(w->name.str() + "g", getw(wires, w), getw(wires, w), getw(wires, w), w);
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break;
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case 10:
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module->addAoi4Gate(w->name.str() + "g", getw(wires, w), getw(wires, w), getw(wires, w), getw(wires, w), w);
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break;
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case 11:
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module->addOai4Gate(w->name.str() + "g", getw(wires, w), getw(wires, w), getw(wires, w), getw(wires, w), w);
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break;
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}
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module->fixup_ports();
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Pass::call(design, "clean");
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ezDefaultSAT ez;
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SigMap sigmap(module);
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SatGen satgen(&ez, &sigmap);
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for (auto c : module->cells()) {
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bool ok = satgen.importCell(c);
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log_assert(ok);
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}
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std::vector<int> in_vec = satgen.importSigSpec(in_sig);
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std::vector<int> inverse_in_vec = ez.vec_not(in_vec);
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std::vector<int> out_vec = satgen.importSigSpec(out_sig);
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for (int i = 0; i < 16; i++)
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{
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std::vector<int> assumptions;
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for (int j = 0; j < SIZE(in_vec); j++)
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assumptions.push_back((i & (1 << j)) ? in_vec.at(j) : inverse_in_vec.at(j));
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std::vector<bool> results;
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if (!ez.solve(out_vec, results, assumptions)) {
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log("No stable solution for input %d found -> recreate module.\n", i);
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goto recreate_module;
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}
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for (int j = 0; j < 4; j++)
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truthtab[i][j] = results[j];
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assumptions.push_back(ez.vec_ne(out_vec, ez.vec_const(results)));
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std::vector<bool> results2;
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if (ez.solve(out_vec, results2, assumptions)) {
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log("Two stable solutions for input %d found -> recreate module.\n", i);
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goto recreate_module;
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}
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}
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break;
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recreate_module:
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design->remove(module);
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}
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log("Found viable UUT after %d cycles:\n", create_cycles);
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Pass::call(design, "write_ilang");
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Pass::call(design, "abc");
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log("\n");
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log("Pre- and post-abc truth table:\n");
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ezDefaultSAT ez;
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SigMap sigmap(module);
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SatGen satgen(&ez, &sigmap);
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for (auto c : module->cells()) {
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bool ok = satgen.importCell(c);
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log_assert(ok);
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}
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std::vector<int> in_vec = satgen.importSigSpec(in_sig);
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std::vector<int> inverse_in_vec = ez.vec_not(in_vec);
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std::vector<int> out_vec = satgen.importSigSpec(out_sig);
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bool found_error = false;
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bool truthtab2[16][4];
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for (int i = 0; i < 16; i++)
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{
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std::vector<int> assumptions;
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for (int j = 0; j < SIZE(in_vec); j++)
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assumptions.push_back((i & (1 << j)) ? in_vec.at(j) : inverse_in_vec.at(j));
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for (int j = 0; j < 4; j++)
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truthtab2[i][j] = truthtab[i][j];
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std::vector<bool> results;
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if (!ez.solve(out_vec, results, assumptions)) {
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log("No stable solution for input %d found.\n", i);
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found_error = true;
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continue;
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}
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for (int j = 0; j < 4; j++)
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truthtab2[i][j] = results[j];
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assumptions.push_back(ez.vec_ne(out_vec, ez.vec_const(results)));
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std::vector<bool> results2;
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if (ez.solve(out_vec, results2, assumptions)) {
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log("Two stable solutions for input %d found -> recreate module.\n", i);
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found_error = true;
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}
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}
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for (int i = 0; i < 16; i++) {
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log("%3d ", i);
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for (int j = 0; j < 4; j++)
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log("%c", truthtab[i][j] ? '1' : '0');
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log(" ");
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for (int j = 0; j < 4; j++)
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log("%c", truthtab2[i][j] ? '1' : '0');
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for (int j = 0; j < 4; j++)
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if (truthtab[i][j] != truthtab2[i][j]) {
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found_error = true;
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log(" !");
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break;
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}
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log("\n");
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}
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log_assert(found_error == false);
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log("\n");
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}
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struct TestAbcloopPass : public Pass {
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TestAbcloopPass() : Pass("test_abcloop", "automatically test handling of loops in abc command") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" test_abcloop [options]\n");
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log("\n");
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log("Test handling of logic loops in ABC.\n");
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log("\n");
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log(" -n {integer}\n");
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log(" create this number of circuits and test them (default = 100).\n");
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log("\n");
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log(" -s {positive_integer}\n");
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log(" use this value as rng seed value (default = unix time).\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design*)
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{
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int num_iter = 100;
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xorshift32_state = 0;
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int argidx;
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for (argidx = 1; argidx < SIZE(args); argidx++)
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{
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if (args[argidx] == "-n" && argidx+1 < SIZE(args)) {
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num_iter = atoi(args[++argidx].c_str());
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continue;
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}
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if (args[argidx] == "-s" && argidx+1 < SIZE(args)) {
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xorshift32_state = atoi(args[++argidx].c_str());
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continue;
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}
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break;
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}
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if (xorshift32_state == 0)
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xorshift32_state = time(NULL) & 0x7fffffff;
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for (int i = 0; i < num_iter; i++)
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test_abcloop();
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}
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} TestAbcloopPass;
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