mirror of https://github.com/YosysHQ/yosys.git
extract_reduce: Fix segfault on "undriven" inputs
This is easily triggered when un-techmapping if the technology-specific cell library isn't loaded. Outputs of technology-specific cells will be seen as inputs, and nets using those outputs will be seen as undriven. Just ignore these cells because they can't be part of a reduce chain anyways.
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@ -160,7 +160,7 @@ struct ExtractReducePass : public Pass
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if (sig_to_sink[a[0]].size() + port_sigs.count(a[0]) == 1)
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{
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Cell* cell_a = sig_to_driver[a[0]];
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if (((cell_a->type == "$_AND_" && gt == GateType::And) ||
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if (cell_a && ((cell_a->type == "$_AND_" && gt == GateType::And) ||
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(cell_a->type == "$_OR_" && gt == GateType::Or) ||
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(cell_a->type == "$_XOR_" && gt == GateType::Xor)))
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{
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@ -177,7 +177,7 @@ struct ExtractReducePass : public Pass
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if (sig_to_sink[b[0]].size() + port_sigs.count(b[0]) == 1)
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{
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Cell* cell_b = sig_to_driver[b[0]];
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if (((cell_b->type == "$_AND_" && gt == GateType::And) ||
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if (cell_b && ((cell_b->type == "$_AND_" && gt == GateType::And) ||
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(cell_b->type == "$_OR_" && gt == GateType::Or) ||
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(cell_b->type == "$_XOR_" && gt == GateType::Xor)))
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{
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