mirror of https://github.com/YosysHQ/yosys.git
Add "dffinit -highlow" and fix synth_intel
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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@ -38,15 +38,25 @@ struct DffinitPass : public Pass {
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log(" operate on the specified cell type. this option can be used\n");
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log(" multiple times.\n");
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log("\n");
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log(" -highlow\n");
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log(" use the string values \"high\" and \"low\" to represent a single-bit\n");
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log(" initial value of 1 or 0. (multi-bit values are not supported in this\n");
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log(" mode.)\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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log_header(design, "Executing DFFINIT pass (set INIT param on FF cells).\n");
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dict<IdString, dict<IdString, IdString>> ff_types;
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bool highlow_mode = false;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-highlow") {
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highlow_mode = true;
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continue;
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}
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if (args[argidx] == "-ff" && argidx+3 < args.size()) {
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IdString cell_name = RTLIL::escape_id(args[++argidx]);
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IdString output_port = RTLIL::escape_id(args[++argidx]);
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@ -106,6 +116,16 @@ struct DffinitPass : public Pass {
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cleanup_bits.insert(sig[i]);
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}
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if (highlow_mode && GetSize(value) != 0) {
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if (GetSize(value) != 1)
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log_error("Multi-bit init value for %s.%s.%s is incompatible with -highlow mode.\n",
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log_id(module), log_id(cell), log_id(it.second));
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if (value[0] == State::S1)
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value = Const("high");
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else
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value = Const("low");
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}
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log("Setting %s.%s.%s (port=%s, net=%s) to %s.\n", log_id(module), log_id(cell), log_id(it.second),
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log_id(it.first), log_signal(sig), log_signal(value));
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cell->setParam(it.second, value);
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@ -219,7 +219,7 @@ struct SynthIntelPass : public ScriptPass {
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run("techmap -map +/intel/cycloneiv/cells_map.v");
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else
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run("techmap -map +/intel/cycloneive/cells_map.v");
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run("dffinit -ff dffeas Q INIT");
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run("dffinit -highlow -ff dffeas q power_up");
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run("clean -purge");
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}
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