mirror of https://github.com/YosysHQ/yosys.git
Bugfix in mapping $tribuf to $_TBUF_
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@ -293,7 +293,7 @@ void simplemap_tribuf(RTLIL::Module *module, RTLIL::Cell *cell)
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RTLIL::Cell *gate = module->addCell(NEW_ID, "$_TBUF_");
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gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src"));
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gate->setPort("\\A", sig_a[i]);
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gate->setPort("\\E", sig_e[i]);
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gate->setPort("\\E", sig_e);
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gate->setPort("\\Y", sig_y[i]);
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}
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}
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