mirror of https://github.com/YosysHQ/yosys.git
Further improved fsm_detect output, attempt to detect self-resetting circuits
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@ -118,6 +118,7 @@ static void detect_fsm(RTLIL::Wire *wire)
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bool has_init_attr = wire->attributes.count("\\init") > 0;
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bool is_module_port = sig_at_port.check_any(assign_map(RTLIL::SigSpec(wire)));
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bool looks_like_state_reg = false, looks_like_good_state_reg = false;
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bool is_self_resetting = false;
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if (has_fsm_encoding_none)
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return;
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@ -142,11 +143,52 @@ static void detect_fsm(RTLIL::Wire *wire)
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pool<Cell*> recursion_monitor;
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RTLIL::SigSpec sig_q = assign_map(cellport.first->getPort("\\Q"));
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RTLIL::SigSpec sig_d = assign_map(cellport.first->getPort("\\D"));
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if (sig_q == RTLIL::SigSpec(wire)) {
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looks_like_state_reg = check_state_mux_tree(sig_q, sig_d, recursion_monitor);
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looks_like_good_state_reg = check_state_users(sig_q);
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if (sig_q != assign_map(wire))
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continue;
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looks_like_state_reg = check_state_mux_tree(sig_q, sig_d, recursion_monitor);
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looks_like_good_state_reg = check_state_users(sig_q);
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if (!looks_like_state_reg)
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break;
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ConstEval ce(wire->module);
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std::set<sig2driver_entry_t> cellport_list;
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sig2user.find(sig_q, cellport_list);
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for (auto &cellport : cellport_list)
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{
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RTLIL::Cell *cell = cellport.first;
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bool set_output = false, clr_output = false;
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if (cell->type == "$ne")
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set_output = true;
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if (cell->type == "$eq")
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clr_output = true;
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if (!set_output && !clr_output) {
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clr_output = true;
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for (auto &port_it : cell->connections())
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if (port_it.first != "\\A" || port_it.first != "\\Y")
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clr_output = false;
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}
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if (set_output || clr_output) {
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for (auto &port_it : cell->connections())
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if (cell->output(port_it.first)) {
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SigSpec sig = assign_map(port_it.second);
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Const val(set_output ? State::S1 : State::S0, GetSize(sig));
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ce.set(sig, val);
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}
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}
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}
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SigSpec sig_y = sig_d, sig_undef;
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if (ce.eval(sig_y, sig_undef))
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is_self_resetting = true;
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}
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if (has_fsm_encoding_attr)
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@ -165,20 +207,40 @@ static void detect_fsm(RTLIL::Wire *wire)
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if (!looks_like_state_reg)
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warnings.push_back("Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!\n");
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if (is_self_resetting)
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warnings.push_back("FSM seems to be self-resetting. Possible simulation-synthesis mismatch!\n");
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if (!warnings.empty()) {
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string warnmsg = stringf("Regarding the user-specified fsm_encoding attribute on %s.%s:\n", log_id(wire->module), log_id(wire));
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for (auto w : warnings) warnmsg += " " + w;
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log_warning("%s", warnmsg.c_str());
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} else {
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log("FSM state register %s in module %s already has fsm_encoding attribute.\n", log_id(wire->module), log_id(wire));
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log("FSM state register %s.%s already has fsm_encoding attribute.\n", log_id(wire->module), log_id(wire));
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}
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}
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else
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if (looks_like_state_reg && looks_like_good_state_reg && !has_init_attr && !is_module_port)
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if (looks_like_state_reg && looks_like_good_state_reg && !has_init_attr && !is_module_port && !is_self_resetting)
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{
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log("Found FSM state register %s in module %s.\n", wire->name.c_str(), module->name.c_str());
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log("Found FSM state register %s.%s.\n", log_id(wire->module), log_id(wire));
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wire->attributes["\\fsm_encoding"] = RTLIL::Const("auto");
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}
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else
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if (looks_like_state_reg)
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{
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log("Not marking %s.%s as FSM state register:\n", log_id(wire->module), log_id(wire));
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if (is_module_port)
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log(" Register is connected to module port.\n");
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if (!looks_like_good_state_reg)
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log(" Users of register don't seem to benefit from recoding.\n");
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if (has_init_attr)
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log(" Register has an initialization value.");
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if (is_self_resetting)
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log(" Circuit seems to be self-resetting.\n");
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}
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}
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struct FsmDetectPass : public Pass {
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