mirror of https://github.com/YosysHQ/yosys.git
Also merge $equiv cells in equiv_struct
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@ -119,6 +119,7 @@ struct EquivStructWorker
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for (auto cell : module->selected_cells())
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if (cell->type == "$equiv") {
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equiv_bits.add(sigmap(cell->getPort("\\A")), sigmap(cell->getPort("\\B")));
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cells_by_type[cell->type].insert(cell->name);
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} else
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if (module->design->selected(module, cell)) {
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if (mode_icells || module->design->module(cell->type))
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