mirror of https://github.com/YosysHQ/yosys.git
Now using BLIF as ABC input format
This commit is contained in:
Clifford Wolf
parent
a582b9d184
commit
be5dab87fd
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@ -21,6 +21,10 @@
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// Berkeley Logic Synthesis and Verification Group, ABC: A System for Sequential Synthesis and Verification
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// http://www.eecs.berkeley.edu/~alanmi/abc/
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// [[CITE]] Berkeley Logic Interchange Format (BLIF)
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// University of California. Berkeley. July 28, 1992
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// http://www.ece.cmu.edu/~ee760/760docs/blif.pdf
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// [[CITE]] Kahn's Topological sorting algorithm
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// Kahn, Arthur B. (1962), "Topological sorting of large networks", Communications of the ACM 5 (11): 558–562, doi:10.1145/368996.369025
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// http://en.wikipedia.org/wiki/Topological_sorting
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@ -339,7 +343,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
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if (!cleanup)
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tempdir_name[0] = tempdir_name[4] = '_';
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char *p = mkdtemp(tempdir_name);
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log_header("Extracting gate netlist of module `%s' to `%s/input.v'..\n", module->name.c_str(), tempdir_name);
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log_header("Extracting gate netlist of module `%s' to `%s/input.blif'..\n", module->name.c_str(), tempdir_name);
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if (p == NULL)
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log_error("For some reason mkdtemp() failed!\n");
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@ -362,60 +366,73 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
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handle_loops();
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if (asprintf(&p, "%s/input.v", tempdir_name) < 0) abort();
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if (asprintf(&p, "%s/input.blif", tempdir_name) < 0) abort();
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FILE *f = fopen(p, "wt");
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if (f == NULL)
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log_error("Opening %s for writing failed: %s\n", p, strerror(errno));
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free(p);
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fprintf(f, "module netlist (");
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bool first = true;
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for (auto &si : signal_list) {
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if (!si.is_port)
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continue;
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if (!first)
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fprintf(f, ", ");
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fprintf(f, "n%d", si.id);
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first = false;
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}
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fprintf(f, "); // %s\n", module->name.c_str());
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fprintf(f, ".model netlist\n");
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int count_input = 0, count_output = 0;
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int count_input = 0;
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fprintf(f, ".inputs");
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for (auto &si : signal_list) {
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if (si.is_port) {
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if (si.type >= 0)
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count_output++;
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else
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count_input++;
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}
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fprintf(f, "%s n%d; // %s\n", si.is_port ? si.type >= 0 ?
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"output" : "input" : "wire", si.id, log_signal(si.sig));
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if (!si.is_port || si.type >= 0)
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continue;
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fprintf(f, " n%d", si.id);
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count_input++;
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}
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fprintf(f, "\n");
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int count_output = 0;
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fprintf(f, ".outputs");
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for (auto &si : signal_list) {
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if (!si.is_port || si.type < 0)
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continue;
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fprintf(f, " n%d", si.id);
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count_output++;
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}
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fprintf(f, "\n");
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for (auto &si : signal_list)
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fprintf(f, "# n%-5d %s\n", si.id, log_signal(si.sig));
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for (auto &si : signal_list) {
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assert(si.sig.width == 1 && si.sig.chunks.size() == 1);
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if (si.sig.chunks[0].wire == NULL)
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fprintf(f, "assign n%d = %c;\n", si.id, si.sig.chunks[0].data.bits[0] == RTLIL::State::S1 ? '1' : '0');
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if (si.sig.chunks[0].wire == NULL) {
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fprintf(f, ".names n%d\n", si.id);
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if (si.sig.chunks[0].data.bits[0] == RTLIL::State::S1)
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fprintf(f, "1\n");
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}
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}
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int count_gates = 0;
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for (auto &si : signal_list) {
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if (si.type == 'n')
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fprintf(f, "not (n%d, n%d);\n", si.id, si.in1);
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else if (si.type == 'a')
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fprintf(f, "and (n%d, n%d, n%d);\n", si.id, si.in1, si.in2);
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else if (si.type == 'o')
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fprintf(f, "or (n%d, n%d, n%d);\n", si.id, si.in1, si.in2);
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else if (si.type == 'x')
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fprintf(f, "xor (n%d, n%d, n%d);\n", si.id, si.in1, si.in2);
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else if (si.type == 'm')
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fprintf(f, "assign n%d = n%d ? n%d : n%d;\n", si.id, si.in3, si.in2, si.in1);
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else if (si.type >= 0)
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if (si.type == 'n') {
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fprintf(f, ".names n%d n%d\n", si.in1, si.id);
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fprintf(f, "0 1\n");
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} else if (si.type == 'a') {
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fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id);
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fprintf(f, "11 1\n");
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} else if (si.type == 'o') {
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fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id);
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fprintf(f, "-1 1\n");
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fprintf(f, "1- 1\n");
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} else if (si.type == 'x') {
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fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id);
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fprintf(f, "01 1\n");
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fprintf(f, "10 1\n");
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} else if (si.type == 'm') {
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fprintf(f, ".names n%d n%d n%d n%d\n", si.in1, si.in2, si.in3, si.id);
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fprintf(f, "1-0 1\n");
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fprintf(f, "-11 1\n");
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} else if (si.type >= 0)
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abort();
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if (si.type >= 0)
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count_gates++;
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}
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fprintf(f, "endmodule\n");
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fprintf(f, ".end\n");
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fclose(f);
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log("Extracted %d gates and %zd wires to a netlist network with %d inputs and %d outputs.\n",
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@ -456,7 +473,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
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int buffer_pos = 0;
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if (!liberty_file.empty()) {
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buffer_pos += snprintf(buffer+buffer_pos, 1024-buffer_pos,
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"%s -s -c 'read_verilog %s/input.v; read_lib %s; ",
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"%s -s -c 'read_blif %s/input.blif; read_lib %s; ",
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exe_file.c_str(), tempdir_name, liberty_file.c_str());
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if (!constr_file.empty())
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buffer_pos += snprintf(buffer+buffer_pos, 1024-buffer_pos,
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@ -469,16 +486,16 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
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} else
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if (!script_file.empty())
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buffer_pos += snprintf(buffer+buffer_pos, 1024-buffer_pos,
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"%s -s -c 'read_verilog %s/input.v; source %s; ",
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"%s -s -c 'read_blif %s/input.blif; source %s; ",
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exe_file.c_str(), tempdir_name, script_file.c_str());
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else
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if (lut_mode)
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buffer_pos += snprintf(buffer+buffer_pos, 1024-buffer_pos,
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"%s -s -c 'read_verilog %s/input.v; read_lut %s/lutdefs.txt; strash; balance; dch; if; ",
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"%s -s -c 'read_blif %s/input.blif; read_lut %s/lutdefs.txt; strash; balance; dch; if; ",
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exe_file.c_str(), tempdir_name, tempdir_name);
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else
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buffer_pos += snprintf(buffer+buffer_pos, 1024-buffer_pos,
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"%s -s -c 'read_verilog %s/input.v; read_library %s/stdcells.genlib; strash; balance; dch; map; ",
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"%s -s -c 'read_blif %s/input.blif; read_library %s/stdcells.genlib; strash; balance; dch; map; ",
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exe_file.c_str(), tempdir_name, tempdir_name);
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buffer_pos += snprintf(buffer+buffer_pos, 1024-buffer_pos, "write_blif %s/output.blif' 2>&1", tempdir_name);
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