mirror of https://github.com/YosysHQ/yosys.git
Added some additional checks to techmap
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@ -293,11 +293,16 @@ struct TechmapWorker
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bool keep_running = true;
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techmap_do_cache[tpl] = true;
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std::set<std::string> techmap_wire_names;
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while (keep_running)
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{
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TechmapWires twd = techmap_find_special_wires(tpl);
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keep_running = false;
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for (auto &it : twd)
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techmap_wire_names.insert(it.first);
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for (auto &it : twd["_TECHMAP_FAIL_"]) {
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RTLIL::SigSpec value = it.value;
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if (value.is_fully_const() && value.as_bool()) {
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@ -320,7 +325,9 @@ struct TechmapWorker
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if (!data.value.is_fully_const())
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log_error("Techmap yielded config wire %s with non-const value %s.\n", RTLIL::id2cstr(data.wire->name), log_signal(data.value));
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techmap_wire_names.erase(it.first);
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tpl->wires.erase(data.wire->name);
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const char *p = data.wire->name.c_str();
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const char *q = strrchr(p+1, '.');
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q = q ? q : p+1;
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@ -335,10 +342,13 @@ struct TechmapWorker
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std::string cmd_string = data.value.as_const().decode_string();
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RTLIL::Selection tpl_mod_sel(false);
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std::string backup_active_module = map->selected_active_module;
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map->selected_active_module = tpl->name;
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tpl_mod_sel.select(tpl);
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map->selection_stack.push_back(tpl_mod_sel);
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Pass::call(map, cmd_string);
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map->selection_stack.pop_back();
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map->selected_active_module = backup_active_module;
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keep_running = true;
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break;
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@ -353,7 +363,11 @@ struct TechmapWorker
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for (auto &it2 : it.second)
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if (!it2.value.is_fully_const())
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log_error("Techmap yielded config wire %s with non-const value %s.\n", RTLIL::id2cstr(it2.wire->name), log_signal(it2.value));
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techmap_wire_names.erase(it.first);
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}
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for (auto &it : techmap_wire_names)
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log_error("Techmap special wire %s disappeared. This is considered a fatal error.\n", RTLIL::id2cstr(it));
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}
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if (techmap_do_cache.at(tpl) == false)
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