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Added extract -verbose and -map ilang support

This commit is contained in:
Clifford Wolf 2013-02-27 17:26:32 +01:00
parent f28b6aff40
commit da3d55a29c
1 changed files with 15 additions and 5 deletions
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20
passes/extract/extract.cc
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@ -185,6 +185,7 @@ struct ExtractPass : public Pass {
log_push();
std::string filename;
bool verbose;
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {
@ -192,21 +193,33 @@ struct ExtractPass : public Pass {
filename = args[++argidx];
continue;
}
if (args[argidx] == "-verbose") {
verbose = true;
continue;
}
break;
}
extra_args(args, argidx, design);
if (filename.empty())
log_cmd_error("Missing option -map <verilog_file>.\n");
log_cmd_error("Missing option -map <verilog_or_ilang_file>.\n");
RTLIL::Design *map = new RTLIL::Design;
FILE *f = fopen(filename.c_str(), "rt");
if (f == NULL)
log_error("Can't open map file `%s'\n", filename.c_str());
Frontend::frontend_call(map, f, filename, "verilog");
if (filename.size() > 3 && filename.substr(filename.size()-3) == ".il")
Frontend::frontend_call(map, f, filename, "ilang");
else
Frontend::frontend_call(map, f, filename, "verilog");
fclose(f);
SubCircuit::Solver solver;
std::vector<SubCircuit::Solver::Result> results;
if (verbose)
solver.setVerbose();
std::map<std::string, RTLIL::Module*> needle_map, haystack_map;
log_header("Creating graphs for SubCircuit library.\n");
@ -233,9 +246,6 @@ struct ExtractPass : public Pass {
log_header("Running solver from SubCircuit library.\n");
solver.setVerbose();
std::vector<SubCircuit::Solver::Result> results;
for (auto &needle_it : needle_map)
for (auto &haystack_it : haystack_map) {
log("Solving for %s in %s.\n", needle_it.first.c_str(), haystack_it.first.c_str());