mirror of https://github.com/YosysHQ/yosys.git
Only prefer connected signals iff they have public names
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@ -112,11 +112,12 @@ static bool compare_signals(RTLIL::SigSpec &s1, RTLIL::SigSpec &s2, SigPool ®
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if (w1->port_input != w2->port_input)
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return w2->port_input;
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if (regs.check_any(s1) != regs.check_any(s2))
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return regs.check_any(s2);
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if (conns.check_any(s1) != conns.check_any(s2))
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return conns.check_any(s2);
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if (w1->name[0] == '\\' && w2->name[0] == '\\') {
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if (regs.check_any(s1) != regs.check_any(s2))
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return regs.check_any(s2);
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if (conns.check_any(s1) != conns.check_any(s2))
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return conns.check_any(s2);
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}
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if (w1->port_output != w2->port_output)
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return w2->port_output;
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