mirror of https://github.com/YosysHQ/yosys.git
ABC to read_box before reading netlist
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@ -322,7 +322,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
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log_header(design, "Extracting gate netlist of module `%s' to `%s/input.xaig'..\n",
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module->name.c_str(), replace_tempdir(tempdir_name, tempdir_name, show_tempdir).c_str());
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std::string abc_script = stringf("&read %s/input.xaig; &ps ", tempdir_name.c_str());
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std::string abc_script;
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if (!liberty_file.empty()) {
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abc_script += stringf("read_lib -w %s; ", liberty_file.c_str());
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@ -343,6 +343,8 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
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else
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abc_script += stringf("read_library %s/stdcells.genlib; ", tempdir_name.c_str());
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abc_script += stringf("&read %s/input.xaig; &ps ", tempdir_name.c_str());
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if (!script_file.empty()) {
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if (script_file[0] == '+') {
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for (size_t i = 1; i < script_file.size(); i++)
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