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Don't be too smart with $dff cells with "init" attribute on out signal
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@ -83,7 +83,7 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
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val_init.bits.push_back(bit.wire == NULL ? bit.data : RTLIL::State::Sx);
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}
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if (dff->type == "$dff" && mux_drivers.has(sig_d)) {
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if (dff->type == "$dff" && mux_drivers.has(sig_d) && !has_init) {
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std::set<RTLIL::Cell*> muxes;
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mux_drivers.find(sig_d, muxes);
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for (auto mux : muxes) {
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