mirror of https://github.com/YosysHQ/yosys.git
Some cleanups in opt_clean
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3838856a9e
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66eb254fc2
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@ -35,18 +35,15 @@ int count_rm_cells, count_rm_wires;
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void rmunused_module_cells(RTLIL::Module *module, bool verbose)
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{
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SigMap assign_map(module);
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SigMap sigmap(module);
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std::set<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> queue, unused;
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SigSet<RTLIL::Cell*> wire2driver;
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for (auto &it : module->cells_) {
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RTLIL::Cell *cell = it.second;
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for (auto &it2 : cell->connections()) {
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if (!ct.cell_input(cell->type, it2.first)) {
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RTLIL::SigSpec sig = it2.second;
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assign_map.apply(sig);
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wire2driver.insert(sig, cell);
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}
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if (!ct.cell_input(cell->type, it2.first))
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wire2driver.insert(sigmap(it2.second), cell);
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}
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if (cell->type == "$memwr" || cell->type == "$assert" || cell->has_keep_attr())
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queue.insert(cell);
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@ -57,15 +54,13 @@ void rmunused_module_cells(RTLIL::Module *module, bool verbose)
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RTLIL::Wire *wire = it.second;
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if (wire->port_output || wire->get_bool_attribute("\\keep")) {
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std::set<RTLIL::Cell*> cell_list;
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RTLIL::SigSpec sig = RTLIL::SigSpec(wire);
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assign_map.apply(sig);
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wire2driver.find(sig, cell_list);
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wire2driver.find(sigmap(wire), cell_list);
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for (auto cell : cell_list)
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queue.insert(cell);
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}
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}
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while (queue.size() > 0)
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while (!queue.empty())
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{
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std::set<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> new_queue;
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for (auto cell : queue)
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@ -74,12 +69,10 @@ void rmunused_module_cells(RTLIL::Module *module, bool verbose)
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for (auto &it : cell->connections()) {
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if (!ct.cell_output(cell->type, it.first)) {
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std::set<RTLIL::Cell*> cell_list;
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RTLIL::SigSpec sig = it.second;
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assign_map.apply(sig);
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wire2driver.find(sig, cell_list);
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for (auto cell : cell_list) {
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if (unused.count(cell) > 0)
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new_queue.insert(cell);
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wire2driver.find(sigmap(it.second), cell_list);
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for (auto c : cell_list) {
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if (unused.count(c))
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new_queue.insert(c);
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}
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}
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}
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