mirror of https://github.com/YosysHQ/yosys.git
Added "test_cell -noeval"
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@ -552,6 +552,9 @@ struct TestCellPass : public Pass {
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log(" -nosat\n");
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log(" do not check SAT model or run SAT equivalence checking\n");
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log("\n");
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log(" -noeval\n");
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log(" do not check const-eval models\n");
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log("\n");
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log(" -v\n");
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log(" print additional debug information to the console\n");
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log("\n");
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@ -570,6 +573,7 @@ struct TestCellPass : public Pass {
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bool verbose = false;
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bool constmode = false;
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bool nosat = false;
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bool noeval = false;
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int argidx;
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for (argidx = 1; argidx < GetSize(args); argidx++)
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@ -619,6 +623,10 @@ struct TestCellPass : public Pass {
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nosat = true;
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continue;
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}
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if (args[argidx] == "-noeval") {
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noeval = true;
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continue;
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}
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if (args[argidx] == "-v") {
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verbose = true;
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continue;
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@ -772,7 +780,8 @@ struct TestCellPass : public Pass {
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Backend::backend_call(design, &vlog_file, "<test_cell -vlog>", "verilog -selected -noexpr");
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uut_names.push_back(uut_name);
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}
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run_eval_test(design, verbose, nosat, uut_name, vlog_file);
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if (!noeval)
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run_eval_test(design, verbose, nosat, uut_name, vlog_file);
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}
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delete design;
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}
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