mirror of https://github.com/YosysHQ/yosys.git
flowmap: new techmap pass.
This commit is contained in:
whitequark
parent
56ca1e6afc
commit
07af772a72
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@ -6,12 +6,12 @@ OBJS += passes/opt/opt_reduce.o
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OBJS += passes/opt/opt_rmdff.o
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OBJS += passes/opt/opt_clean.o
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OBJS += passes/opt/opt_expr.o
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OBJS += passes/opt/opt_lut.o
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ifneq ($(SMALL),1)
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OBJS += passes/opt/share.o
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OBJS += passes/opt/wreduce.o
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OBJS += passes/opt/opt_demorgan.o
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OBJS += passes/opt/rmports.o
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OBJS += passes/opt/opt_lut.o
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endif
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@ -36,6 +36,7 @@ OBJS += passes/techmap/attrmvcp.o
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OBJS += passes/techmap/attrmap.o
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OBJS += passes/techmap/zinit.o
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OBJS += passes/techmap/dff2dffs.o
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OBJS += passes/techmap/flowmap.o
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endif
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GENFILES += passes/techmap/techmap.inc
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@ -0,0 +1,873 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2018 whitequark <whitequark@whitequark.org>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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// [[CITE]]
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// Jason Cong; Yuzheng Ding, "An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs,"
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// Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 13, no. 1, Jan 1994
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// doi: 10.1109/43.273754
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// Required reading material:
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//
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// Min-cut max-flow theorem:
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// https://www.coursera.org/lecture/algorithms-part2/maxflow-mincut-theorem-beb9G
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// FlowMap paper:
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// http://cadlab.cs.ucla.edu/~cong/papers/iccad92.pdf
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// Notes on implementation:
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//
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// 1. In the paper, the nodes are logic elements (analogous to Yosys cells) and edges are wires. However, in our implementation, we use
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// an inverted approach: the nodes are Yosys wire bits, and the edges are derived from (but aren't represented by) Yosys cells.
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// This may seem counterintuitive. Three observations may help understanding this. First, for a cell with a 1-bit Y output that is
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// the sole driver of its output net (which is the typical case), these representations are equivalent, because there is an exact
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// correspondence between cells and output wires. Second, in the paper, primary inputs (analogous to Yosys cell or module ports) are
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// nodes, and in Yosys, inputs are wires; our approach allows a direct mapping from both primary inputs and 1-output logic elements to
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// flow graph nodes. Third, Yosys cells may have multiple outputs or multi-bit outputs, and by using Yosys wire bits as flow graph nodes,
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// such cells are supported without any additional effort; any Yosys cell with n output wire bits ends up being split into n flow graph
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// nodes.
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//
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// 2. The paper introduces three networks: Nt, Nt', and Nt''. The network Nt is directly represented by a subgraph of RTLIL graph,
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// which is parsed into an equivalent but easier to traverse representation in FlowmapWorker. The network Nt' is built explicitly
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// from a subgraph of Nt, and uses a similar representation in FlowGraph. The network Nt'' is implicit in FlowGraph, which is possible
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// because of the following observation: each Nt' node corresponds to an Nt'' edge of capacity 1, and each Nt' edge corresponds to
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// an Nt'' edge of capacity ∞. Therefore, we only need to explicitly record flow for Nt' edges and through Nt' nodes.
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//
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// 3. The paper ambiguously states: "Moreover, we can find such a cut (X′′, X̅′′) by performing a depth first search starting at the source s,
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// and including in X′′ all the nodes which are reachable from s." This actually refers to a specific kind of search, mincut computation.
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// Mincut computation involves computing the set of nodes reachable from s by an undirected path with no full (i.e. zero capacity) forward
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// edges or empty (i.e. no flow) backward edges.
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/modtools.h"
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#include "kernel/consteval.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct GraphStyle
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{
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string label;
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string color;
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GraphStyle(string label = "", string color = "black") :
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label(label), color(color) {}
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};
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static string dot_escape(string value)
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{
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std::string escaped;
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for (char c : value) {
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if (c == '\n')
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{
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escaped += "\\n";
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continue;
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}
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if (c == '\\' || c == '"')
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escaped += "\\";
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escaped += c;
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}
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return escaped;
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}
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static void dump_dot_graph(string filename,
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pool<RTLIL::SigBit> nodes, dict<RTLIL::SigBit, pool<RTLIL::SigBit>> edges,
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pool<RTLIL::SigBit> inputs, pool<RTLIL::SigBit> outputs,
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std::function<GraphStyle(RTLIL::SigBit)> node_style =
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[](RTLIL::SigBit) { return GraphStyle{}; },
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std::function<GraphStyle(RTLIL::SigBit, RTLIL::SigBit)> edge_style =
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[](RTLIL::SigBit, RTLIL::SigBit) { return GraphStyle{}; },
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string name = "")
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{
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FILE *f = fopen(filename.c_str(), "w");
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fprintf(f, "digraph \"%s\" {\n", name.c_str());
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fprintf(f, " rankdir=\"TB\";\n");
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dict<RTLIL::SigBit, int> ids;
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for (auto node : nodes)
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{
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ids[node] = ids.size();
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string shape = "ellipse";
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if (inputs[node])
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shape = "box";
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if (outputs[node])
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shape = "octagon";
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auto prop = node_style(node);
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string id;
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if (node == SigBit())
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id = "(source)";
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else
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id = log_signal(node);
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fprintf(f, " n%d [ shape=%s, fontname=\"Monospace\", label=\"%s%s\", color=\"%s\" ];\n",
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ids[node], shape.c_str(), dot_escape(id).c_str(), dot_escape(prop.label.c_str()).c_str(), prop.color.c_str());
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}
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fprintf(f, " { rank=\"source\"; ");
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for (auto input : inputs)
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if (nodes[input])
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fprintf(f, "n%d; ", ids[input]);
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fprintf(f, "}\n");
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fprintf(f, " { rank=\"sink\"; ");
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for (auto output : outputs)
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if (nodes[output])
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fprintf(f, "n%d; ", ids[output]);
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fprintf(f, "}\n");
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for (auto edge : edges)
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{
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auto source = edge.first;
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for (auto sink : edge.second) {
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if (nodes[source] && nodes[sink])
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{
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auto prop = edge_style(source, sink);
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fprintf(f, " n%d -> n%d [ label=\"%s\", color=\"%s\" ];\n",
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ids[source], ids[sink], dot_escape(prop.label.c_str()).c_str(), prop.color.c_str());
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}
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}
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}
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fprintf(f, "}\n");
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fclose(f);
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}
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struct FlowGraph
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{
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const RTLIL::SigBit source;
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RTLIL::SigBit sink;
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pool<RTLIL::SigBit> nodes = {source};
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dict<RTLIL::SigBit, pool<RTLIL::SigBit>> edges_fw, edges_bw;
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const int MAX_NODE_FLOW = 1;
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dict<RTLIL::SigBit, int> node_flow;
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dict<pair<RTLIL::SigBit, RTLIL::SigBit>, int> edge_flow;
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dict<RTLIL::SigBit, pool<RTLIL::SigBit>> collapsed;
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void dump_dot_graph(string filename)
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{
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auto node_style = [&](RTLIL::SigBit node) {
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string label;
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for (auto collapsed_node : collapsed[node])
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label += stringf(" %s", log_signal(collapsed_node));
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int flow = node_flow[node];
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if (node != source && node != sink)
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label += stringf("\n%d/%d", flow, MAX_NODE_FLOW);
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else
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label += stringf("\n%d/∞", flow);
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return GraphStyle{label, flow < MAX_NODE_FLOW ? "green" : "black"};
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};
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auto edge_style = [&](RTLIL::SigBit source, RTLIL::SigBit sink) {
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int flow = edge_flow[{source, sink}];
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return GraphStyle{stringf("%d/∞", flow), flow > 0 ? "blue" : "black"};
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};
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::dump_dot_graph(filename, nodes, edges_fw, {source}, {sink}, node_style, edge_style);
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}
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// Here, we are working on the Nt'' network, but our representation is the Nt' network.
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// The difference between these is that where in Nt' we have a subgraph:
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//
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// v1 -> v2 -> v3
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//
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// in Nt'' we have a corresponding subgraph:
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//
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// v'1b -∞-> v'2t -f-> v'2b -∞-> v'3t
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//
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// To address this, we split each node v into two nodes, v't and v'b. This representation is virtual,
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// in the sense that nodes v't and v'b are overlaid on top of the original node v, and only exist
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// in paths and worklists.
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struct NodePrime
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{
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RTLIL::SigBit node;
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bool is_bottom;
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NodePrime(RTLIL::SigBit node, bool is_bottom) :
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node(node), is_bottom(is_bottom) {}
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bool operator==(const NodePrime &other) const
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{
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return node == other.node && is_bottom == other.is_bottom;
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}
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bool operator!=(const NodePrime &other) const
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{
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return !(*this == other);
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}
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unsigned int hash() const
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{
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return hash_ops<pair<RTLIL::SigBit, int>>::hash({node, is_bottom});
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}
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static NodePrime top(RTLIL::SigBit node)
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{
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return NodePrime(node, /*is_bottom=*/false);
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}
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static NodePrime bottom(RTLIL::SigBit node)
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{
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return NodePrime(node, /*is_bottom=*/true);
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}
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NodePrime as_top() const
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{
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log_assert(is_bottom);
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return top(node);
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}
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NodePrime as_bottom() const
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{
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log_assert(!is_bottom);
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return bottom(node);
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}
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};
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bool find_augmenting_path(bool commit)
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{
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NodePrime source_prime = {source, true};
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NodePrime sink_prime = {sink, false};
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vector<NodePrime> path = {source_prime};
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pool<NodePrime> visited = {};
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bool found;
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do {
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found = false;
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auto node_prime = path.back();
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visited.insert(node_prime);
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if (!node_prime.is_bottom) // vt
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{
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if (!visited[node_prime.as_bottom()] && node_flow[node_prime.node] < MAX_NODE_FLOW)
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{
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path.push_back(node_prime.as_bottom());
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found = true;
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}
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else
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{
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for (auto node_pred : edges_bw[node_prime.node])
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{
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if (!visited[NodePrime::bottom(node_pred)] && edge_flow[{node_pred, node_prime.node}] > 0)
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{
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path.push_back(NodePrime::bottom(node_pred));
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found = true;
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break;
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}
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}
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}
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}
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else // vb
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{
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if (!visited[node_prime.as_top()] && node_flow[node_prime.node] > 0)
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{
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path.push_back(node_prime.as_top());
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found = true;
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}
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else
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{
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for (auto node_succ : edges_fw[node_prime.node])
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{
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if (!visited[NodePrime::top(node_succ)] /* && edge_flow[...] < ∞ */)
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{
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path.push_back(NodePrime::top(node_succ));
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found = true;
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break;
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}
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}
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}
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}
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if (!found && path.size() > 1)
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{
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path.pop_back();
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found = true;
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}
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} while(path.back() != sink_prime && found);
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if (commit && path.back() == sink_prime)
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{
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auto prev_prime = path.front();
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for (auto node_prime : path)
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{
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if (node_prime == source_prime)
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continue;
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log_assert(prev_prime.is_bottom ^ node_prime.is_bottom);
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if (prev_prime.node == node_prime.node)
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{
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auto node = node_prime.node;
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if (!prev_prime.is_bottom && node_prime.is_bottom)
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{
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log_assert(node_flow[node] == 0);
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node_flow[node]++;
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}
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else
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{
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log_assert(node_flow[node] != 0);
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node_flow[node]--;
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}
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}
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else
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{
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if (prev_prime.is_bottom && !node_prime.is_bottom)
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{
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log_assert(true /* edge_flow[...] < ∞ */);
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edge_flow[{prev_prime.node, node_prime.node}]++;
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}
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else
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{
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log_assert((edge_flow[{node_prime.node, prev_prime.node}] > 0));
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edge_flow[{node_prime.node, prev_prime.node}]--;
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}
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}
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prev_prime = node_prime;
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}
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node_flow[source]++;
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node_flow[sink]++;
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}
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return path.back() == sink_prime;
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}
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int maximum_flow(int order)
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{
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int flow = 0;
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while (flow < order && find_augmenting_path(/*commit=*/true))
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flow++;
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return flow + find_augmenting_path(/*commit=*/false);
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}
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pair<pool<RTLIL::SigBit>, pool<RTLIL::SigBit>> edge_cut()
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{
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pool<RTLIL::SigBit> x, xi;
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NodePrime source_prime = {source, true};
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NodePrime sink_prime = {sink, false};
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pool<NodePrime> worklist = {source_prime}, visited;
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while (!worklist.empty())
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{
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auto node_prime = worklist.pop();
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if (visited[node_prime])
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continue;
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visited.insert(node_prime);
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if (!node_prime.is_bottom)
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x.insert(node_prime.node);
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// Mincut is constructed by traversing a graph in an undirected way along forward edges that aren't full, or backward edges
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// that aren't empty.
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if (!node_prime.is_bottom) // top
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{
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if (node_flow[node_prime.node] < MAX_NODE_FLOW)
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worklist.insert(node_prime.as_bottom());
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for (auto node_pred : edges_bw[node_prime.node])
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if (edge_flow[{node_pred, node_prime.node}] > 0)
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worklist.insert(NodePrime::bottom(node_pred));
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}
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else // bottom
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{
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if (node_flow[node_prime.node] > 0)
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worklist.insert(node_prime.as_top());
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for (auto node_succ : edges_fw[node_prime.node])
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if (true /* edge_flow[...] < ∞ */)
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worklist.insert(NodePrime::top(node_succ));
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}
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}
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for (auto node : nodes)
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if (!x[node])
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xi.insert(node);
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for (auto collapsed_node : collapsed[sink])
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xi.insert(collapsed_node);
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log_assert(!x[sink] && xi[sink]);
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return {x, xi};
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}
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};
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struct FlowmapWorker
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{
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int order;
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pool<IdString> cell_types;
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bool debug;
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RTLIL::Module *module;
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SigMap sigmap;
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ModIndex index;
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pool<RTLIL::Cell*> cells;
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pool<RTLIL::SigBit> nodes, inputs, outputs;
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dict<RTLIL::SigBit, pool<RTLIL::SigBit>> edges_fw, edges_bw;
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dict<RTLIL::SigBit, int> labels;
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dict<RTLIL::SigBit, pool<RTLIL::SigBit>> lut_gates, lut_inputs;
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dict<RTLIL::SigBit, ModIndex::PortInfo> node_origins;
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dict<RTLIL::Cell*, pool<RTLIL::SigBit>> cell_fanout;
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int mapped_count = 0, packed_count = 0, unique_packed_count = 0;
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void dump_dot_graph(string filename, pool<RTLIL::SigBit> subgraph = {}, pair<pool<RTLIL::SigBit>, pool<RTLIL::SigBit>> cut = {})
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{
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if (subgraph.empty())
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subgraph = nodes;
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auto node_style = [&](RTLIL::SigBit node) {
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string label, color;
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if (labels[node] == -1)
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label = string("\n<unlabeled>");
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else
|
||||
label = stringf("\nl=%d", labels[node]);
|
||||
color = "black";
|
||||
if (cut.first[node])
|
||||
color = "blue";
|
||||
if (cut.second[node])
|
||||
color = "red";
|
||||
return GraphStyle{label, color};
|
||||
};
|
||||
auto edge_style = [&](RTLIL::SigBit, RTLIL::SigBit) {
|
||||
return GraphStyle{};
|
||||
};
|
||||
::dump_dot_graph(filename, subgraph, edges_fw, inputs, outputs, node_style, edge_style, module->name.str());
|
||||
}
|
||||
|
||||
pool<RTLIL::SigBit> find_subgraph(RTLIL::SigBit sink)
|
||||
{
|
||||
pool<RTLIL::SigBit> subgraph;
|
||||
pool<RTLIL::SigBit> worklist = {sink};
|
||||
while (!worklist.empty())
|
||||
{
|
||||
auto node = worklist.pop();
|
||||
subgraph.insert(node);
|
||||
for (auto source : edges_bw[node])
|
||||
{
|
||||
if (!subgraph[source])
|
||||
worklist.insert(source);
|
||||
}
|
||||
}
|
||||
return subgraph;
|
||||
}
|
||||
|
||||
FlowGraph build_flow_graph(RTLIL::SigBit sink, int p)
|
||||
{
|
||||
FlowGraph flow_graph;
|
||||
flow_graph.sink = sink;
|
||||
|
||||
pool<RTLIL::SigBit> worklist = {sink}, visited;
|
||||
while (!worklist.empty())
|
||||
{
|
||||
auto node = worklist.pop();
|
||||
visited.insert(node);
|
||||
|
||||
auto collapsed_node = labels[node] == p ? sink : node;
|
||||
if (node != collapsed_node)
|
||||
flow_graph.collapsed[collapsed_node].insert(node);
|
||||
flow_graph.nodes.insert(collapsed_node);
|
||||
|
||||
for (auto node_pred : edges_bw[node])
|
||||
{
|
||||
auto collapsed_node_pred = labels[node_pred] == p ? sink : node_pred;
|
||||
if (node_pred != collapsed_node_pred)
|
||||
flow_graph.collapsed[collapsed_node_pred].insert(node_pred);
|
||||
if (collapsed_node != collapsed_node_pred)
|
||||
{
|
||||
flow_graph.edges_bw[collapsed_node].insert(collapsed_node_pred);
|
||||
flow_graph.edges_fw[collapsed_node_pred].insert(collapsed_node);
|
||||
}
|
||||
if (inputs[node_pred])
|
||||
{
|
||||
flow_graph.edges_bw[collapsed_node_pred].insert(flow_graph.source);
|
||||
flow_graph.edges_fw[flow_graph.source].insert(collapsed_node_pred);
|
||||
}
|
||||
|
||||
if (!visited[node_pred])
|
||||
worklist.insert(node_pred);
|
||||
}
|
||||
}
|
||||
return flow_graph;
|
||||
}
|
||||
|
||||
FlowmapWorker(int order, pool<IdString> cell_types, bool debug, RTLIL::Module *module) :
|
||||
order(order), cell_types(cell_types), debug(debug), module(module), sigmap(module), index(module)
|
||||
{
|
||||
log("Labeling cells.\n");
|
||||
for (auto cell : module->selected_cells())
|
||||
{
|
||||
if (cell_types[cell->type])
|
||||
{
|
||||
if (!cell->known())
|
||||
{
|
||||
log_error("Cell %s (%s.%s) is unknown.\n", cell->type.c_str(), log_id(module), log_id(cell));
|
||||
}
|
||||
cells.insert(cell);
|
||||
|
||||
for (auto conn : cell->connections())
|
||||
{
|
||||
if (!cell->output(conn.first)) continue;
|
||||
int offset = -1;
|
||||
for (auto bit : conn.second)
|
||||
{
|
||||
offset++;
|
||||
if (!bit.wire) continue;
|
||||
auto mapped_bit = sigmap(bit);
|
||||
if (nodes[mapped_bit])
|
||||
log_error("Multiple drivers found for wire %s.\n", log_signal(mapped_bit));
|
||||
nodes.insert(mapped_bit);
|
||||
node_origins[mapped_bit] = ModIndex::PortInfo(cell, conn.first, offset);
|
||||
cell_fanout[cell].insert(mapped_bit);
|
||||
}
|
||||
}
|
||||
|
||||
int fanin = 0;
|
||||
for (auto conn : cell->connections())
|
||||
{
|
||||
if (!cell->input(conn.first)) continue;
|
||||
for (auto bit : sigmap(conn.second))
|
||||
{
|
||||
if (!bit.wire) continue;
|
||||
for (auto fanout_bit : cell_fanout[cell])
|
||||
{
|
||||
edges_fw[bit].insert(fanout_bit);
|
||||
edges_bw[fanout_bit].insert(bit);
|
||||
}
|
||||
fanin++;
|
||||
}
|
||||
}
|
||||
|
||||
if (fanin > order)
|
||||
log_error("Cell %s (%s.%s) with fan-in %d cannot be mapped to a %d-LUT.\n",
|
||||
cell->type.c_str(), log_id(module), log_id(cell), fanin, order);
|
||||
}
|
||||
}
|
||||
|
||||
for (auto edge : edges_fw)
|
||||
{
|
||||
if (!nodes[edge.first])
|
||||
{
|
||||
inputs.insert(edge.first);
|
||||
nodes.insert(edge.first);
|
||||
}
|
||||
}
|
||||
|
||||
for (auto node : nodes)
|
||||
{
|
||||
auto node_info = index.query(node);
|
||||
if (node_info->is_output && !inputs[node])
|
||||
outputs.insert(node);
|
||||
for (auto port : node_info->ports)
|
||||
if (!cell_types[port.cell->type] && !inputs[node])
|
||||
outputs.insert(node);
|
||||
}
|
||||
|
||||
for (auto node : nodes)
|
||||
labels[node] = -1;
|
||||
for (auto input : inputs)
|
||||
labels[input] = 0;
|
||||
|
||||
if (debug)
|
||||
{
|
||||
dump_dot_graph("flowmap-init.dot");
|
||||
log("Dumped complete combinatorial graph to `flowmap-init.dot`.\n");
|
||||
}
|
||||
|
||||
pool<RTLIL::SigBit> worklist = nodes;
|
||||
int debug_num = 0;
|
||||
while (!worklist.empty())
|
||||
{
|
||||
auto sink = worklist.pop();
|
||||
if (labels[sink] != -1)
|
||||
continue;
|
||||
|
||||
bool inputs_have_labels = true;
|
||||
for (auto sink_input : edges_bw[sink])
|
||||
{
|
||||
if (labels[sink_input] == -1)
|
||||
{
|
||||
inputs_have_labels = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (!inputs_have_labels)
|
||||
continue;
|
||||
|
||||
if (debug)
|
||||
{
|
||||
debug_num++;
|
||||
log("Examining subgraph %d rooted in %s.\n", debug_num, log_signal(sink));
|
||||
}
|
||||
|
||||
pool<RTLIL::SigBit> subgraph = find_subgraph(sink);
|
||||
|
||||
int p = 1;
|
||||
for (auto subgraph_node : subgraph)
|
||||
p = max(p, labels[subgraph_node]);
|
||||
|
||||
FlowGraph flow_graph = build_flow_graph(sink, p);
|
||||
int flow = flow_graph.maximum_flow(order);
|
||||
pool<RTLIL::SigBit> x, xi;
|
||||
if (flow <= order)
|
||||
{
|
||||
labels[sink] = p;
|
||||
auto cut = flow_graph.edge_cut();
|
||||
x = cut.first;
|
||||
xi = cut.second;
|
||||
}
|
||||
else
|
||||
{
|
||||
labels[sink] = p + 1;
|
||||
x = subgraph;
|
||||
x.erase(sink);
|
||||
xi.insert(sink);
|
||||
}
|
||||
lut_gates[sink] = xi;
|
||||
|
||||
pool<RTLIL::SigBit> k;
|
||||
for (auto xi_node : xi)
|
||||
{
|
||||
for (auto xi_node_pred : edges_bw[xi_node])
|
||||
if (x[xi_node_pred])
|
||||
k.insert(xi_node_pred);
|
||||
}
|
||||
log_assert((int)k.size() <= order);
|
||||
lut_inputs[sink] = k;
|
||||
|
||||
if (debug)
|
||||
{
|
||||
log(" Maximum flow: %d. Assigned label %d.\n", flow, labels[sink]);
|
||||
dump_dot_graph(stringf("flowmap-%d-sub.dot", debug_num), subgraph, {x, xi});
|
||||
log(" Dumped subgraph to `flowmap-%d-sub.dot`.\n", debug_num);
|
||||
flow_graph.dump_dot_graph(stringf("flowmap-%d-flow.dot", debug_num));
|
||||
log(" Dumped flow graph to `flowmap-%d-flow.dot`.\n", debug_num);
|
||||
log(" LUT packed:");
|
||||
for (auto xi_node : xi)
|
||||
log(" %s", log_signal(xi_node));
|
||||
log(".\n");
|
||||
log(" LUT inputs:");
|
||||
for (auto k_node : k)
|
||||
log(" %s", log_signal(k_node));
|
||||
log(".\n");
|
||||
}
|
||||
|
||||
for (auto sink_succ : edges_fw[sink])
|
||||
worklist.insert(sink_succ);
|
||||
}
|
||||
|
||||
if (debug)
|
||||
{
|
||||
dump_dot_graph("flowmap-done.dot");
|
||||
log("Dumped complete combinatorial graph to `flowmap-done.dot`.\n");
|
||||
}
|
||||
|
||||
int depth = 0;
|
||||
for (auto label : labels)
|
||||
depth = max(depth, label.second);
|
||||
log("Maximum depth: %d levels.\n", depth);
|
||||
|
||||
ConstEval ce(module);
|
||||
for (auto input_node : inputs)
|
||||
ce.stop(input_node);
|
||||
|
||||
log("\n");
|
||||
log("Mapping cells.\n");
|
||||
|
||||
pool<RTLIL::SigBit> mapped_nodes;
|
||||
worklist = outputs;
|
||||
while (!worklist.empty())
|
||||
{
|
||||
auto node = worklist.pop();
|
||||
if (node_origins.count(node))
|
||||
{
|
||||
auto origin = node_origins[node];
|
||||
if (origin.cell->getPort(origin.port).size() == 1)
|
||||
log("Mapping %s.%s.%s (%s).\n",
|
||||
log_id(module), log_id(origin.cell), origin.port.c_str(), log_signal(node));
|
||||
else
|
||||
log("Mapping %s.%s.%s [%d] (%s).\n",
|
||||
log_id(module), log_id(origin.cell), origin.port.c_str(), origin.offset, log_signal(node));
|
||||
}
|
||||
else
|
||||
{
|
||||
log("Mapping %s.%s.\n", log_id(module), log_signal(node));
|
||||
}
|
||||
|
||||
for (auto gate_node : lut_gates[node])
|
||||
{
|
||||
log_assert(node_origins.count(gate_node));
|
||||
|
||||
if (gate_node == node)
|
||||
continue;
|
||||
|
||||
auto gate_origin = node_origins[gate_node];
|
||||
if (gate_origin.cell->getPort(gate_origin.port).size() == 1)
|
||||
log(" Packing %s.%s.%s (%s).\n",
|
||||
log_id(module), log_id(gate_origin.cell), gate_origin.port.c_str(), log_signal(gate_node));
|
||||
else
|
||||
log(" Packing %s.%s.%s [%d] (%s).\n",
|
||||
log_id(module), log_id(gate_origin.cell), gate_origin.port.c_str(), gate_origin.offset, log_signal(gate_node));
|
||||
}
|
||||
|
||||
vector<RTLIL::SigBit> input_nodes(lut_inputs[node].begin(), lut_inputs[node].end());
|
||||
RTLIL::Const lut_table(State::Sx, 1 << input_nodes.size());
|
||||
for (unsigned i = 0; i < (1 << input_nodes.size()); i++)
|
||||
{
|
||||
ce.push();
|
||||
for (size_t n = 0; n < input_nodes.size(); n++)
|
||||
ce.set(input_nodes[n], ((i >> n) & 1) ? State::S1 : State::S0);
|
||||
|
||||
RTLIL::SigSpec value = node, undef;
|
||||
if (!ce.eval(value, undef))
|
||||
{
|
||||
string env;
|
||||
for (auto input_node : input_nodes)
|
||||
env += stringf(" %s = %s\n", log_signal(input_node), log_signal(ce.values_map(input_node)));
|
||||
log_error("Cannot evaluate %s because %s is not defined.\nEvaluation environment:\n%s",
|
||||
log_signal(node), log_signal(undef), env.c_str());
|
||||
}
|
||||
|
||||
lut_table[i] = value.as_bool() ? State::S1 : State::S0;
|
||||
ce.pop();
|
||||
}
|
||||
|
||||
RTLIL::SigSpec lut_a, lut_y = node;
|
||||
for (auto input_node : input_nodes)
|
||||
lut_a.append_bit(input_node);
|
||||
|
||||
RTLIL::Cell *lut = module->addLut(NEW_ID, lut_a, lut_y, lut_table);
|
||||
mapped_count++;
|
||||
|
||||
for (auto gate_node : lut_gates[node])
|
||||
{
|
||||
auto gate_origin = node_origins[gate_node];
|
||||
lut->add_strpool_attribute("\\src", gate_origin.cell->get_strpool_attribute("\\src"));
|
||||
packed_count++;
|
||||
}
|
||||
|
||||
log(" Packed into a %d-LUT %s.%s.\n", (int)input_nodes.size(), log_id(module), log_id(lut));
|
||||
|
||||
mapped_nodes.insert(node);
|
||||
for (auto input_node : input_nodes)
|
||||
{
|
||||
if (!mapped_nodes[input_node] && !inputs[input_node])
|
||||
worklist.insert(input_node);
|
||||
}
|
||||
}
|
||||
|
||||
unique_packed_count += nodes.size();
|
||||
|
||||
for (auto node : mapped_nodes)
|
||||
{
|
||||
auto origin = node_origins[node];
|
||||
RTLIL::SigSpec driver = origin.cell->getPort(origin.port);
|
||||
driver[origin.offset] = module->addWire(NEW_ID);
|
||||
origin.cell->setPort(origin.port, driver);
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
static void split(std::vector<std::string> &tokens, const std::string &text, char sep)
|
||||
{
|
||||
size_t start = 0, end = 0;
|
||||
while ((end = text.find(sep, start)) != std::string::npos) {
|
||||
tokens.push_back(text.substr(start, end - start));
|
||||
start = end + 1;
|
||||
}
|
||||
tokens.push_back(text.substr(start));
|
||||
}
|
||||
|
||||
struct FlowmapPass : public Pass {
|
||||
FlowmapPass() : Pass("flowmap", "pack LUTs with FlowMap") { }
|
||||
void help() YS_OVERRIDE
|
||||
{
|
||||
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
||||
log("\n");
|
||||
log(" flowmap [options] [selection]\n");
|
||||
log("\n");
|
||||
log("This pass uses the FlowMap technology mapping algorithm to pack logic gates\n");
|
||||
log("into k-LUTs with optimal depth. It allows mapping any circuit elements that can\n");
|
||||
log("be evaluated with the `eval` pass, including cells with multiple output ports\n");
|
||||
log("and multi-bit input and output ports.\n");
|
||||
log("\n");
|
||||
log(" -maxlut <k>\n");
|
||||
log(" perform technology mapping for a k-LUT architecture. if not specified,\n");
|
||||
log(" defaults to 3.\n");
|
||||
log("\n");
|
||||
log(" -cells <cell>[,<cell>,...]\n");
|
||||
log(" map specified cells. if not specified, maps $_NOT_, $_AND_, $_OR_,\n");
|
||||
log(" $_XOR_ and $_MUX_, which are the outputs of the `simplemap` pass.\n");
|
||||
log("\n");
|
||||
log(" -debug\n");
|
||||
log(" dump intermediate graphs.\n");
|
||||
log("\n");
|
||||
}
|
||||
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
|
||||
{
|
||||
log_header(design, "Executing FLOWMAP pass (pack LUTs with FlowMap).\n");
|
||||
|
||||
int order = 3;
|
||||
vector<string> cells;
|
||||
bool debug = false;
|
||||
|
||||
size_t argidx;
|
||||
for (argidx = 1; argidx < args.size(); argidx++)
|
||||
{
|
||||
if (args[argidx] == "-maxlut" && argidx + 1 < args.size())
|
||||
{
|
||||
order = atoi(args[++argidx].c_str());
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-cells" && argidx + 1 < args.size())
|
||||
{
|
||||
split(cells, args[++argidx], ',');
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-debug")
|
||||
{
|
||||
debug = true;
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
}
|
||||
extra_args(args, argidx, design);
|
||||
|
||||
pool<IdString> cell_types;
|
||||
if (!cells.empty())
|
||||
{
|
||||
for (auto &cell : cells)
|
||||
cell_types.insert(cell);
|
||||
}
|
||||
else
|
||||
{
|
||||
cell_types = {"$_NOT_", "$_AND_", "$_OR_", "$_XOR_", "$_MUX_"};
|
||||
}
|
||||
|
||||
int mapped_count = 0, packed_count = 0, unique_packed_count = 0;
|
||||
for (auto module : design->selected_modules())
|
||||
{
|
||||
FlowmapWorker worker(order, cell_types, debug, module);
|
||||
mapped_count += worker.mapped_count;
|
||||
packed_count += worker.packed_count;
|
||||
unique_packed_count += worker.unique_packed_count;
|
||||
}
|
||||
|
||||
log("\n");
|
||||
log("Mapped %d LUTs.\n", mapped_count);
|
||||
log("Packed %d cells %d times.\n", unique_packed_count, packed_count);
|
||||
}
|
||||
} FlowmapPass;
|
||||
|
||||
PRIVATE_NAMESPACE_END
|
||||
Loading…
Reference in New Issue